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tillitis-key/hw/application_fpga/tb
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Jonas Thörnblad a330aa15ec
Add verilog file for TRNG simulation
2024-11-28 16:10:00 +01:00
..
application_fpga_sim.v Rename top level simulation files 2024-11-12 15:33:33 +01:00
application_fpga_verilator.cc Raise bps to 62500 2022-10-21 14:10:41 +02:00
reset_gen_sim.v Align module name with its file name. 2024-11-28 16:09:59 +01:00
trng_sim.v Add verilog file for TRNG simulation 2024-11-28 16:10:00 +01:00