tillitis-key/hw/application_fpga/tb
Jonas Thörnblad 8f2f312531
fpga/fw: Resize ROM and FW_RAM, add RESETINFO partition
In order to be able to leave data for firmware signalling the
intention with a reset or to leave data for the next app in a chain of
apps, we introduce a part of FW_RAM that can be used to store this
data. In order to do this, we:

- Change size of ROM from 6 KB to 8 KB.
- Change size of FW_RAM, from 2 KB to 4 KB.
- Add RESETINFO memory partition inside FW_RAM.
- Add generation of map file.
- Change CFLAGS from using -O2 to using -Os.
- Update address ranges for valid access to ROM and FW_RAM.
- Move stack to be located before data+bss and the RESETINFO data
  above them. This also means we introduce hardware stack overflow
  protection through the Security Monitor.
- Revise firmware README to the new use of FW_RAM.
2025-02-21 11:15:34 +01:00
..
application_fpga_sim.v fpga/fw: Resize ROM and FW_RAM, add RESETINFO partition 2025-02-21 11:15:34 +01:00
application_fpga_verilator.cc fpga: Introduce CTS signals for UART 2025-02-11 13:50:04 +01:00
reset_gen_sim.v Align module name with its file name. 2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v fpga: Introduce CTS signals for UART 2025-02-11 13:50:04 +01:00
trng_sim.v Add verilog file for TRNG simulation 2024-11-28 16:10:00 +01:00