390 lines
12 KiB
Verilog
390 lines
12 KiB
Verilog
//======================================================================
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//
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// tb_uart.v
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// ---------
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// Testbench for the UART core.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (c) 2014, Secworks Sweden AB
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or
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// without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//======================================================================
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module tb_uart();
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter DEBUG = 0;
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parameter VERBOSE = 0;
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parameter CLK_HALF_PERIOD = 1;
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parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
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//----------------------------------------------------------------
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// Register and Wire declarations.
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//----------------------------------------------------------------
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reg [31 : 0] cycle_ctr;
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reg [31 : 0] error_ctr;
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reg [31 : 0] tc_ctr;
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reg tb_clk;
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reg tb_reset_n;
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reg tb_rxd;
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wire tb_txd;
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wire tb_rxd_syn;
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wire [7 : 0] tb_rxd_data;
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wire tb_rxd_ack;
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wire tb_txd_syn;
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wire [7 : 0] tb_txd_data;
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wire tb_txd_ack;
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reg tb_cs;
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reg tb_we;
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reg [7 : 0] tb_address;
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reg [31 : 0] tb_write_data;
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wire [31 : 0] tb_read_data;
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wire tb_error;
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wire [7 : 0] tb_debug;
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reg txd_state;
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//----------------------------------------------------------------
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// Device Under Test.
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//----------------------------------------------------------------
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uart dut(
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.clk(tb_clk),
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.reset_n(tb_reset_n),
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.rxd(tb_rxd),
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.txd(tb_txd),
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.rxd_syn(tb_rxd_syn),
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.rxd_data(tb_rxd_data),
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.rxd_ack(tb_rxd_ack),
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// Internal transmit interface.
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.txd_syn(tb_txd_syn),
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.txd_data(tb_txd_data),
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.txd_ack(tb_txd_ack),
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// API interface.
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.cs(tb_cs),
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.we(tb_we),
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.address(tb_address),
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.write_data(tb_write_data),
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.read_data(tb_read_data),
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.error(tb_error),
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.debug(tb_debug)
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);
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//----------------------------------------------------------------
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// Concurrent assignments.
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//----------------------------------------------------------------
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// We connect the internal facing ports on the dut together.
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assign tb_txd_syn = tb_rxd_syn;
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assign tb_txd_data = tb_rxd_data;
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assign tb_rxd_ack = tb_txd_ack;
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//----------------------------------------------------------------
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// clk_gen
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//
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// Clock generator process.
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//----------------------------------------------------------------
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always
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begin : clk_gen
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#CLK_HALF_PERIOD tb_clk = !tb_clk;
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end // clk_gen
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//----------------------------------------------------------------
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// sys_monitor
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//----------------------------------------------------------------
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always
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begin : sys_monitor
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#(CLK_PERIOD);
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if (DEBUG)
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begin
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dump_rx_state();
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dump_tx_state();
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$display("");
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end
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if (VERBOSE)
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begin
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$display("cycle: 0x%016x", cycle_ctr);
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end
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cycle_ctr = cycle_ctr + 1;
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end
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//----------------------------------------------------------------
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// tx_monitor
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//
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// Observes what happens on the dut tx port and reports it.
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//----------------------------------------------------------------
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always @*
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begin : tx_monitor
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if ((!tb_txd) && txd_state)
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begin
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$display("txd going low.");
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txd_state = 0;
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end
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if (tb_txd && (!txd_state))
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begin
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$display("txd going high");
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txd_state = 1;
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end
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end
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//----------------------------------------------------------------
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// dump_dut_state()
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//
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// Dump the state of the dut when needed.
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//----------------------------------------------------------------
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task dump_dut_state;
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begin
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$display("State of DUT");
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$display("------------");
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$display("Inputs and outputs:");
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$display("rxd = 0x%01x, txd = 0x%01x,",
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dut.core.rxd, dut.core.txd);
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$display("");
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$display("Sample and data registers:");
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$display("rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x",
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dut.core.rxd_reg, dut.core.rxd_byte_reg);
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$display("");
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$display("Counters:");
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$display("rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x",
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dut.core.rxd_bit_ctr_reg, dut.core.rxd_bitrate_ctr_reg);
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$display("");
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$display("Control signals and FSM state:");
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$display("erx_ctrl_reg = 0x%02x",
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dut.core.erx_ctrl_reg);
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$display("");
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// dump_rx_state()
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//
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// Dump the state of the rx engine.
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//----------------------------------------------------------------
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task dump_rx_state;
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begin
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$display("rxd = 0x%01x, rxd_reg = 0x%01x, rxd_byte_reg = 0x%01x, rxd_bit_ctr_reg = 0x%01x, rxd_bitrate_ctr_reg = 0x%02x, rxd_syn = 0x%01x, erx_ctrl_reg = 0x%02x",
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dut.core.rxd, dut.core.rxd_reg, dut.core.rxd_byte_reg, dut.core.rxd_bit_ctr_reg,
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dut.core.rxd_bitrate_ctr_reg, dut.core.rxd_syn, dut.core.erx_ctrl_reg);
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// dump_tx_state()
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//
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// Dump the state of the tx engine.
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//----------------------------------------------------------------
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task dump_tx_state;
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begin
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$display("txd = 0x%01x, txd_reg = 0x%01x, txd_byte_reg = 0x%01x, txd_bit_ctr_reg = 0x%01x, txd_bitrate_ctr_reg = 0x%02x, txd_ack = 0x%01x, etx_ctrl_reg = 0x%02x",
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dut.core.txd, dut.core.txd_reg, dut.core.txd_byte_reg, dut.core.txd_bit_ctr_reg,
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dut.core.txd_bitrate_ctr_reg, dut.core.txd_ack, dut.core.etx_ctrl_reg);
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end
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endtask // dump_dut_state
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//----------------------------------------------------------------
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// reset_dut()
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//----------------------------------------------------------------
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task reset_dut;
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begin
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$display("*** Toggle reset.");
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tb_reset_n = 0;
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#(2 * CLK_PERIOD);
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tb_reset_n = 1;
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end
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endtask // reset_dut
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//----------------------------------------------------------------
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// init_sim()
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//
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// Initialize all counters and testbed functionality as well
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// as setting the DUT inputs to defined values.
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//----------------------------------------------------------------
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task init_sim;
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begin
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cycle_ctr = 0;
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error_ctr = 0;
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tc_ctr = 0;
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tb_clk = 0;
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tb_reset_n = 1;
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tb_rxd = 1;
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tb_cs = 0;
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tb_we = 0;
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tb_address = 8'h00;
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tb_write_data = 32'h00000000;
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txd_state = 1;
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end
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endtask // init_sim
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//----------------------------------------------------------------
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// transmit_byte
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//
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// Transmit a byte of data to the DUT receive port.
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//----------------------------------------------------------------
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task transmit_byte(input [7 : 0] data);
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integer i;
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begin
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$display("*** Transmitting byte 0x%02x to the dut.", data);
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#10;
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// Start bit
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$display("*** Transmitting start bit.");
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tb_rxd = 0;
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#(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
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// Send the bits LSB first.
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for (i = 0 ; i < 8 ; i = i + 1)
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begin
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$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
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tb_rxd = data[i];
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#(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
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end
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// Send two stop bits. I.e. two bit times high (mark) value.
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$display("*** Transmitting two stop bits.");
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tb_rxd = 1;
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#(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS);
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$display("*** End of transmission.");
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end
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endtask // transmit_byte
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//----------------------------------------------------------------
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// check_transmit
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//
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// Transmits a byte and checks that it was captured internally
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// by the dut.
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//----------------------------------------------------------------
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task check_transmit(input [7 : 0] data);
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begin
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tc_ctr = tc_ctr + 1;
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transmit_byte(data);
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if (dut.core.rxd_byte_reg == data)
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begin
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$display("*** Correct data: 0x%01x captured by the dut.",
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dut.core.rxd_byte_reg);
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end
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else
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begin
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$display("*** Incorrect data: 0x%01x captured by the dut Should be: 0x%01x.",
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dut.core.rxd_byte_reg, data);
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error_ctr = error_ctr + 1;
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end
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end
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endtask // check_transmit
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//----------------------------------------------------------------
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// test_transmit
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//
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// Transmit a number of test bytes to the dut.
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//----------------------------------------------------------------
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task test_transmit;
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begin
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check_transmit(8'h55);
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check_transmit(8'h42);
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check_transmit(8'hde);
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check_transmit(8'had);
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end
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endtask // test_transmit
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//----------------------------------------------------------------
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// display_test_result()
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//
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// Display the accumulated test results.
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//----------------------------------------------------------------
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task display_test_result;
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begin
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if (error_ctr == 0)
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begin
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$display("*** All %02d test cases completed successfully", tc_ctr);
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end
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else
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begin
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$display("*** %02d test cases did not complete successfully.", error_ctr);
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end
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end
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endtask // display_test_result
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//----------------------------------------------------------------
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// uart_test
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// The main test functionality.
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//----------------------------------------------------------------
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initial
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begin : uart_test
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$display(" -- Testbench for uart core started --");
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init_sim();
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dump_dut_state();
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reset_dut();
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dump_dut_state();
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test_transmit();
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display_test_result();
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$display("*** Simulation done.");
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$finish;
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end // uart_test
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endmodule // tb_uart
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//======================================================================
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// EOF tb_uart.v
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//======================================================================
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