533 lines
15 KiB
Verilog
533 lines
15 KiB
Verilog
//======================================================================
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//
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// uart_core.v
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// -----------
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// A simple universal asynchronous receiver/transmitter (UART)
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// interface. The interface contains 16 byte wide transmit and
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// receivea buffers and can handle start and stop bits. But in
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// general is rather simple. The primary purpose is as host
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// interface for the coretest design. The core also has a
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// loopback mode to allow testing of a serial link.
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//
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// Note that the UART has a separate API interface to allow
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// a control core to change settings such as speed. But the core
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// has default values to allow it to start operating directly
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// after reset. No config should be needed.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (c) 2014, Secworks Sweden AB
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//
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// SPDX-License-Identifier: BSD-2-Clause
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// Redistribution and use in source and binary forms, with or
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// without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//======================================================================
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module uart_core(
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input wire clk,
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input wire reset_n,
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// Configuration parameters
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input wire [15 : 0] bit_rate,
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input wire [3 : 0] data_bits,
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input wire [1 : 0] stop_bits,
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// External data interface
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input wire rxd,
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output wire txd,
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// Internal receive interface.
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output wire rxd_syn,
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output [7 : 0] rxd_data,
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input wire rxd_ack,
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// Internal transmit interface.
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input wire txd_syn,
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input wire [7 : 0] txd_data,
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output wire txd_ready
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);
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//----------------------------------------------------------------
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// Internal constant and parameter definitions.
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//----------------------------------------------------------------
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parameter ERX_IDLE = 0;
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parameter ERX_START = 1;
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parameter ERX_BITS = 2;
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parameter ERX_STOP = 3;
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parameter ERX_SYN = 4;
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parameter ETX_IDLE = 0;
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parameter ETX_ACK = 1;
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parameter ETX_START = 2;
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parameter ETX_BITS = 3;
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parameter ETX_STOP = 4;
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//----------------------------------------------------------------
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// Registers including update variables and write enable.
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//----------------------------------------------------------------
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reg rxd0_reg;
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reg rxd_reg;
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reg [7 : 0] rxd_byte_reg;
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reg rxd_byte_we;
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reg [4 : 0] rxd_bit_ctr_reg;
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reg [4 : 0] rxd_bit_ctr_new;
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reg rxd_bit_ctr_we;
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reg rxd_bit_ctr_rst;
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reg rxd_bit_ctr_inc;
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reg [15 : 0] rxd_bitrate_ctr_reg;
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reg [15 : 0] rxd_bitrate_ctr_new;
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reg rxd_bitrate_ctr_we;
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reg rxd_bitrate_ctr_rst;
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reg rxd_bitrate_ctr_inc;
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reg rxd_syn_reg;
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reg rxd_syn_new;
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reg rxd_syn_we;
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reg [2 : 0] erx_ctrl_reg;
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reg [2 : 0] erx_ctrl_new;
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reg erx_ctrl_we;
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reg txd_reg;
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reg txd_new;
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reg txd_we;
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reg [7 : 0] txd_byte_reg;
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reg [7 : 0] txd_byte_new;
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reg txd_byte_we;
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reg [4 : 0] txd_bit_ctr_reg;
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reg [4 : 0] txd_bit_ctr_new;
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reg txd_bit_ctr_we;
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reg txd_bit_ctr_rst;
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reg txd_bit_ctr_inc;
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reg [15 : 0] txd_bitrate_ctr_reg;
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reg [15 : 0] txd_bitrate_ctr_new;
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reg txd_bitrate_ctr_we;
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reg txd_bitrate_ctr_rst;
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reg txd_bitrate_ctr_inc;
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reg txd_ready_reg;
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reg txd_ready_new;
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reg txd_ready_we;
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reg [2 : 0] etx_ctrl_reg;
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reg [2 : 0] etx_ctrl_new;
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reg etx_ctrl_we;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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wire [15 : 0] half_bit_rate;
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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assign txd = txd_reg;
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assign rxd_syn = rxd_syn_reg;
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assign rxd_data = rxd_byte_reg;
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assign txd_ready = txd_ready_reg;
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assign half_bit_rate = {1'b0, bit_rate[15 : 1]};
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//----------------------------------------------------------------
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// reg_update
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//
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// Update functionality for all registers in the core.
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// All registers are positive edge triggered with
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// synchronous active low reset.
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin: reg_update
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if (!reset_n) begin
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rxd0_reg <= 1'b0;
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rxd_reg <= 1'b0;
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rxd_byte_reg <= 8'h0;
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rxd_bit_ctr_reg <= 5'h0;
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rxd_bitrate_ctr_reg <= 16'h0;
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rxd_syn_reg <= 0;
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erx_ctrl_reg <= ERX_IDLE;
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txd_reg <= 1'b1;
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txd_byte_reg <= 8'h0;
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txd_bit_ctr_reg <= 5'h0;
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txd_bitrate_ctr_reg <= 16'h0;
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txd_ready_reg <= 1'b1;
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etx_ctrl_reg <= ETX_IDLE;
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end
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else begin
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rxd0_reg <= rxd;
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rxd_reg <= rxd0_reg;
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if (rxd_byte_we) begin
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rxd_byte_reg <= {rxd_reg, rxd_byte_reg[7 : 1]};
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end
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if (rxd_bit_ctr_we) begin
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rxd_bit_ctr_reg <= rxd_bit_ctr_new;
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end
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if (rxd_bitrate_ctr_we) begin
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rxd_bitrate_ctr_reg <= rxd_bitrate_ctr_new;
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end
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if (rxd_syn_we) begin
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rxd_syn_reg <= rxd_syn_new;
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end
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if (erx_ctrl_we) begin
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erx_ctrl_reg <= erx_ctrl_new;
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end
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if (txd_we) begin
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txd_reg <= txd_new;
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end
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if (txd_byte_we) begin
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txd_byte_reg <= txd_byte_new;
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end
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if (txd_bit_ctr_we) begin
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txd_bit_ctr_reg <= txd_bit_ctr_new;
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end
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if (txd_bitrate_ctr_we) begin
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txd_bitrate_ctr_reg <= txd_bitrate_ctr_new;
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end
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if (txd_ready_we) begin
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txd_ready_reg <= txd_ready_new;
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end
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if (etx_ctrl_we) begin
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etx_ctrl_reg <= etx_ctrl_new;
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end
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end
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end // reg_update
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//----------------------------------------------------------------
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// rxd_bit_ctr
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//
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// Bit counter for receiving data on the external
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// serial interface.
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//----------------------------------------------------------------
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always @*
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begin: rxd_bit_ctr
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rxd_bit_ctr_new = 5'h0;
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rxd_bit_ctr_we = 1'b0;
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if (rxd_bit_ctr_rst) begin
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rxd_bit_ctr_new = 5'h0;
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rxd_bit_ctr_we = 1'b1;
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end
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else if (rxd_bit_ctr_inc) begin
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rxd_bit_ctr_new = rxd_bit_ctr_reg + 1'h1;
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rxd_bit_ctr_we = 1'b1;
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end
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end // rxd_bit_ctr
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//----------------------------------------------------------------
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// rxd_bitrate_ctr
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//
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// Bitrate counter for receiving data on the external
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// serial interface.
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//----------------------------------------------------------------
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always @*
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begin: rxd_bitrate_ctr
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rxd_bitrate_ctr_new = 16'h0;
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rxd_bitrate_ctr_we = 1'h0;
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if (rxd_bitrate_ctr_rst) begin
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rxd_bitrate_ctr_new = 16'h0;
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rxd_bitrate_ctr_we = 1'b1;
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end
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else if (rxd_bitrate_ctr_inc) begin
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rxd_bitrate_ctr_new = rxd_bitrate_ctr_reg + 1'h1;
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rxd_bitrate_ctr_we = 1'b1;
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end
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end // rxd_bitrate_ctr
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//----------------------------------------------------------------
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// txd_bit_ctr
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//
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// Bit counter for transmitting data on the external
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// serial interface.
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//----------------------------------------------------------------
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always @*
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begin: txd_bit_ctr
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txd_bit_ctr_new = 5'h0;
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txd_bit_ctr_we = 1'h0;
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if (txd_bit_ctr_rst) begin
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txd_bit_ctr_new = 5'h0;
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txd_bit_ctr_we = 1'h1;
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end
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else if (txd_bit_ctr_inc) begin
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txd_bit_ctr_new = txd_bit_ctr_reg + 1'h1;
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txd_bit_ctr_we = 1'b1;
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end
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end // txd_bit_ctr
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//----------------------------------------------------------------
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// txd_bitrate_ctr
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//
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// Bitrate counter for transmitting data on the external
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// serial interface.
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//----------------------------------------------------------------
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always @*
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begin: txd_bitrate_ctr
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txd_bitrate_ctr_new = 16'h0;
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txd_bitrate_ctr_we = 0;
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if (txd_bitrate_ctr_rst) begin
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txd_bitrate_ctr_new = 16'h0;
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txd_bitrate_ctr_we = 1;
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end
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else if (txd_bitrate_ctr_inc) begin
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txd_bitrate_ctr_new = txd_bitrate_ctr_reg + 1'h1;
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txd_bitrate_ctr_we = 1;
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end
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end // txd_bitrate_ctr
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//----------------------------------------------------------------
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// external_rx_engine
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//
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// Logic that implements the receive engine towards
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// the external interface. Detects incoming data, collects it,
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// if required checks parity and store correct data into
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// the rx buffer.
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//----------------------------------------------------------------
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always @*
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begin: external_rx_engine
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rxd_bit_ctr_rst = 0;
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rxd_bit_ctr_inc = 0;
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rxd_bitrate_ctr_rst = 0;
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rxd_bitrate_ctr_inc = 0;
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rxd_byte_we = 0;
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rxd_syn_new = 0;
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rxd_syn_we = 0;
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erx_ctrl_new = ERX_IDLE;
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erx_ctrl_we = 0;
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case (erx_ctrl_reg)
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ERX_IDLE: begin
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if (!rxd_reg) begin
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// Possible start bit detected.
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rxd_bitrate_ctr_rst = 1;
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erx_ctrl_new = ERX_START;
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erx_ctrl_we = 1;
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end
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end
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ERX_START: begin
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rxd_bitrate_ctr_inc = 1;
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if (rxd_reg) begin
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// Just a glitch.
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erx_ctrl_new = ERX_IDLE;
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erx_ctrl_we = 1;
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end
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else begin
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if (rxd_bitrate_ctr_reg == half_bit_rate) begin
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// start bit assumed. We start sampling data.
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rxd_bit_ctr_rst = 1;
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rxd_bitrate_ctr_rst = 1;
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erx_ctrl_new = ERX_BITS;
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erx_ctrl_we = 1;
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end
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end
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end
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ERX_BITS: begin
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if (rxd_bitrate_ctr_reg < bit_rate) begin
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rxd_bitrate_ctr_inc = 1;
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end
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else begin
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rxd_byte_we = 1;
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rxd_bit_ctr_inc = 1;
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rxd_bitrate_ctr_rst = 1;
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if (rxd_bit_ctr_reg == data_bits - 1) begin
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erx_ctrl_new = ERX_STOP;
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erx_ctrl_we = 1;
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end
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end
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end
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ERX_STOP: begin
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rxd_bitrate_ctr_inc = 1;
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if (rxd_bitrate_ctr_reg == bit_rate * stop_bits) begin
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rxd_syn_new = 1;
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rxd_syn_we = 1;
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erx_ctrl_new = ERX_SYN;
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erx_ctrl_we = 1;
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end
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end
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ERX_SYN: begin
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if (rxd_ack) begin
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rxd_syn_new = 0;
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rxd_syn_we = 1;
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erx_ctrl_new = ERX_IDLE;
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erx_ctrl_we = 1;
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end
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end
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default: begin
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end
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endcase // case (erx_ctrl_reg)
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end // external_rx_engine
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//----------------------------------------------------------------
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// external_tx_engine
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//
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// Logic that implements the transmit engine towards
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// the external interface.
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//----------------------------------------------------------------
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always @*
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begin: external_tx_engine
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txd_new = 0;
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txd_we = 0;
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txd_byte_new = 0;
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txd_byte_we = 0;
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txd_bit_ctr_rst = 0;
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txd_bit_ctr_inc = 0;
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txd_bitrate_ctr_rst = 0;
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txd_bitrate_ctr_inc = 0;
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txd_ready_new = 0;
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txd_ready_we = 0;
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etx_ctrl_new = ETX_IDLE;
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etx_ctrl_we = 0;
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case (etx_ctrl_reg)
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ETX_IDLE: begin
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txd_new = 1;
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txd_we = 1;
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if (txd_syn) begin
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txd_byte_new = txd_data;
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txd_byte_we = 1;
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txd_ready_new = 0;
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txd_ready_we = 1;
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txd_bitrate_ctr_rst = 1;
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etx_ctrl_new = ETX_ACK;
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etx_ctrl_we = 1;
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end
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end
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ETX_ACK: begin
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if (!txd_syn) begin
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txd_new = 0;
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txd_we = 1;
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etx_ctrl_new = ETX_START;
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etx_ctrl_we = 1;
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end
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end
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ETX_START: begin
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if (txd_bitrate_ctr_reg == bit_rate) begin
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txd_bit_ctr_rst = 1;
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etx_ctrl_new = ETX_BITS;
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etx_ctrl_we = 1;
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end
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else begin
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txd_bitrate_ctr_inc = 1;
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end
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end
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ETX_BITS: begin
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if (txd_bitrate_ctr_reg < bit_rate) begin
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txd_bitrate_ctr_inc = 1;
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end
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else begin
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txd_bitrate_ctr_rst = 1;
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if (txd_bit_ctr_reg == data_bits) begin
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txd_new = 1;
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txd_we = 1;
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etx_ctrl_new = ETX_STOP;
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etx_ctrl_we = 1;
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end
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else begin
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txd_new = txd_byte_reg[txd_bit_ctr_reg];
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txd_we = 1;
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txd_bit_ctr_inc = 1;
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end
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end
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end
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ETX_STOP: begin
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txd_bitrate_ctr_inc = 1;
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if (txd_bitrate_ctr_reg == bit_rate * stop_bits) begin
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txd_ready_new = 1;
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txd_ready_we = 1;
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etx_ctrl_new = ETX_IDLE;
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etx_ctrl_we = 1;
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end
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end
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default: begin
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end
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endcase // case (etx_ctrl_reg)
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end // external_tx_engine
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endmodule // uart
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//======================================================================
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// EOF uart.v
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//======================================================================
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