tillitis-key/hw/application_fpga/core/timer/README.md
2022-09-19 08:51:11 +02:00

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# timer
A simple timer with prescaler written in Verilog.
## Introduction
This core implements a simple timer with a prescaler. The purpose of the prescaler is to more easily time durations rather than cycles. If for example setting the timer to the clock frequency, the timer can cound seconds.