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tillitis-key/hw/application_fpga/core/timer
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Joachim Strömbergson 6d8c0aff64
(fpga) Update README with info on the free running mode. 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-15 12:43:30 +02:00
..
rtl (fpga) Fix reset, add self checking test case. 2024-08-15 12:21:37 +02:00
tb (fpga) Add testcase for free running mode. 2024-08-15 12:34:55 +02:00
toolruns Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
README.md (fpga) Update README with info on the free running mode. 2024-08-15 12:43:30 +02:00

README.md

timer

Timer with prescaler and support for free running mode.

Introduction

This core implements a simple timer with a prescaler and support for a free running mode.

The prescaler allows measurement of time durations rather than cycles. If for example setting the prescaler to the clock frequency in Hertz, the timer will count seconds. After (prescaler * timer) number of cycles the timer will stop. Checking status of the timer can be done by reading the STATUS_RUNNING_BIT. If set to zero, the timer has completed.

If the free running mode is set (default off), the counter will not stup when the number of cycles defined by (prescaler * timer) has been reached. Instead the timer continues until the CTRL_STOP_BIT is asserted. Note that in free running mode, the ADDR_PRESCALER shall be set to one (1).

API

The following addresses define the API for the timer:

	ADDR_CTRL:          0x08
	CTRL_START_BIT:     0
	CTRL_STOP_BIT:      1

	ADDR_STATUS:        0x09
	STATUS_RUNNING_BIT: 0

	ADDR_PRESCALER:     0x0a
	ADDR_TIMER:         0x0b

	ADDR_FREE_RUNNING:  0x0c
	FREE_RUNNING_BIT    0