Mikael Ågren 62dba7c4fe

PoC: Control access to FW RAM ...

Allow FW RAM access only in the following execution contexts:
- Firmware mode
- IRQ_SYSCALL_HI

Input port `system_mode` of the `fw_ram` module is replaced with an
enable port. Since access to FW RAM not longer depend only on
system_mode

2025-02-07 12:54:01 +01:00

..

application_fpga_sim.v

PoC: Control access to FW RAM

2025-02-07 12:54:01 +01:00

application_fpga_verilator.cc

Updated application_fpga_verilator.cc to match module application_fpga_sim.

2024-11-28 16:10:01 +01:00

reset_gen_sim.v

Align module name with its file name.

2024-11-28 16:09:59 +01:00

tb_application_fpga_sim.v

PoC: Control access to FW RAM

2025-02-07 12:54:01 +01:00

trng_sim.v

Add verilog file for TRNG simulation

2024-11-28 16:10:00 +01:00