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tillitis-key/hw/application_fpga/core
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Joachim Strömbergson 35052e50cb
FPGA: Move RAM address and data scrambling into the RAM module. 
Move the logic implementing the RAM address and data
	scrambling, descrambling into the RAM module. This cleans up
	the top level, and makes it easier to change the scrambling
	without chaning the top. In order to do correct scrambling the
	address to the RAM core must be 16 bits, not 15.

	Clean up some minor details at the top level, fixing text
        aligment and grouping of ports in instances.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>
2024-08-30 10:53:13 +02:00
..
clk_reset_gen Doc: Add README for the clock and reset core. 2024-08-29 16:06:59 +02:00
fw_ram Doc: Add README for the fw_ram. 2024-08-29 16:06:59 +02:00
picorv32 FPGA: Ignore warnings about blocking assignment in clocked processes 2024-06-17 15:37:13 +02:00
ram FPGA: Move RAM address and data scrambling into the RAM module. 2024-08-30 10:53:13 +02:00
rom Doc: Add README for the ROM core. 2024-08-29 16:06:59 +02:00
timer Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
tk1 FPGA: Add system reset API 2024-08-20 13:25:22 +02:00
touch_sense Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
trng Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00
uart FPGA: Increase clock frequency to 21 MHz 2024-08-20 13:45:00 +02:00
uds Update Verilog version to 2005 for linting 2024-04-24 08:44:08 +02:00