Mikael Ågren 5e15b40a86 PoC: PicoRV32 interrupts ... A proof-of-concept of enabling PicoRV32 interrupts. Two interrupt sources, which can be triggered by writes to memory addresses, are added. The design has only been simulated, not run on hardware. Synthesis: Ice40 LC utilization is 93% (4934/5280) when built using tkey-builder:4 Simulation: A `tb_application_fpga_irqpoc` target is added. Running `make tb_application_fpga_irqpoc` creates `tb_application_fpga_sim.fst` which can be inspected in GTKWave or Surfer. Firmware: A simple firmware is added in `fw/irqpoc`. It enables both interrupts and triggers each interrupt once. Custom PicoRV32 instructions are located in `custom_ops.S`. It is imported from upstream PicoRV32 commit: 70f3c33ac8		2025-02-12 11:08:15 +01:00
..
application_fpga_sim.v	PoC: PicoRV32 interrupts	2025-02-12 11:08:15 +01:00
application_fpga_verilator.cc	fpga: Introduce CTS signals for UART	2025-02-11 13:50:04 +01:00
reset_gen_sim.v	Align module name with its file name.	2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v	PoC: PicoRV32 interrupts	2025-02-12 11:08:15 +01:00
trng_sim.v	Add verilog file for TRNG simulation	2024-11-28 16:10:00 +01:00