Daniel Jobson 2ec2196e92

PoC: Make sensitive assets only readable/writable before system_mode is set ...

After the first time system_mode is set to one, the assets will no
longer be read- or writeable, even if system_mode is set to zero at a
later syscall. This is to make sure syscalls does not have the same
privilege as the firmware has at first boot.

We need to monitor when system_mode is set to one, otherwise we might
accedentially lock the assets before actually leaving firmware, for
example if firmware would use a function set in any of the registers
used in system_mode_ctrl.

Co-authored-by: Mikael Ågren <mikael@tillitis.se>

2025-02-07 12:54:02 +01:00

..

application_fpga_sim.v

PoC: Make sensitive assets only readable/writable before system_mode is set

2025-02-07 12:54:02 +01:00

application_fpga_verilator.cc

Updated application_fpga_verilator.cc to match module application_fpga_sim.

2024-11-28 16:10:01 +01:00

reset_gen_sim.v

Align module name with its file name.

2024-11-28 16:09:59 +01:00

tb_application_fpga_sim.v

PoC: Add example firmware with embedded that calls syscalls implemented in C

2025-02-07 12:54:01 +01:00

trng_sim.v

Add verilog file for TRNG simulation

2024-11-28 16:10:00 +01:00