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tillitis-key/hw/application_fpga/core/uart/rtl
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blaufish cced6aec31
Explicity make uart_core.rx_data a wire (#140)
2023-08-16 10:43:04 +02:00
..
uart_core.v Explicity make uart_core.rx_data a wire (#140) 2023-08-16 10:43:04 +02:00
uart_fifo.v Add API address to read out number of bytes in Rx FIFO 2023-03-07 08:22:27 +01:00
uart.v Add API address to read out number of bytes in Rx FIFO 2023-03-07 08:22:27 +01:00