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https://github.com/tillitis/tillitis-key1.git
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143 lines
3.9 KiB
Verilog
143 lines
3.9 KiB
Verilog
//======================================================================
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//
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// ram.v
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// -----
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// Module that encapsulates the four SPRAM blocks in the Lattice
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// iCE40UP 5K device. This creates a single 32-bit wide,
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// 128 kByte large memory.
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module ram(
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input wire clk,
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input wire reset_n,
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input wire cs,
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input wire [03 : 0] we,
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input wire [14 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg ready_reg;
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reg cs0;
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reg cs1;
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reg [31 : 0] read_data0;
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reg [31 : 0] read_data1;
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reg [31 : 0] muxed_read_data;
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//----------------------------------------------------------------
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// Concurrent assignment of ports.
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//----------------------------------------------------------------
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assign read_data = muxed_read_data;
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assign ready = ready_reg;
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//----------------------------------------------------------------
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// SPRAM instances.
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//----------------------------------------------------------------
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SB_SPRAM256KA spram0(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[15:0]),
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.MASKWREN({we[1], we[1], we[0], we[0]}),
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.WREN(we[1] | we[0]),
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.CHIPSELECT(cs0),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data0[15:0])
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);
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SB_SPRAM256KA spram1(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[31:16]),
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.MASKWREN({we[3], we[3], we[2], we[2]}),
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.WREN(we[3] | we[2]),
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.CHIPSELECT(cs0),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data0[31:16])
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);
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SB_SPRAM256KA spram2(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[15:0]),
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.MASKWREN({we[1], we[1], we[0], we[0]}),
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.WREN(we[1] | we[0]),
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.CHIPSELECT(cs1),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data1[15:0])
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);
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SB_SPRAM256KA spram3(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[31:16]),
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.MASKWREN({we[3], we[3], we[2], we[2]}),
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.WREN(we[3] | we[2]),
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.CHIPSELECT(cs1),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data1[31:16])
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);
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//----------------------------------------------------------------
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// reg_update
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//
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// Posedge triggered with synchronous, active low reset.
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// This simply creates a one cycle access latency to match
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// the latency of the spram blocks.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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//----------------------------------------------------------------
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// mem_mux
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//----------------------------------------------------------------
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always @*
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begin : mem_mux
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cs0 = ~address[14] & cs;
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cs1 = address[14] & cs;
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if (address[14]) begin
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muxed_read_data = read_data1;
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end else begin
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muxed_read_data = read_data0;
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end
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end
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endmodule // ram
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//======================================================================
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// EOF ram.v
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//======================================================================
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