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59 lines
2.2 KiB
Markdown
59 lines
2.2 KiB
Markdown
# Threat model
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## Introduction
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The Tillitis TKey is a platform for running secure applications in a
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restricted execution environment physically separate from the device
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host. The secure applications provide functionality and controlled
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access to derived secrets on the device. The purpose of the device is
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to solve typical end user authentication problems.
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This document describes the threat model for device. Based on the
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system description and use cases, the threat model tries to capture and
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describe the threats that needs to be mitigated in order for the
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device to meet its purpose and objectives.
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## Version information
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The threat model will get updated and expanded for each release.
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### engineering-release-1
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This is an early release aimed at developers interested
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in writing applications for Tillitis TKey. The design allows easy access to
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the board, and is even shipped with a programmer to download new FPGA bitstreams.
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#### Known weakneses
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The bitstream, which includes the Unique Device Secret (UDS) as well as the firmware
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implementing the measured boot are stored as part of the bitstream in an external
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Flash memory connected to the FPFGA.
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The CH552 MCU providing USB host communication contains FW that implements the UART
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communication with the FPGA. The firmware can be updated by performing *port knocking*.
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The knock sequence is to apply 3.3V through a 10k resistor to the D+ line,
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while powering on the device.
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There may be possible buffer overflows via the USB host interface to the FW of the CH552,
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allowing both execution and modification of the FW CH552.
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#### Out of scope
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- All physical and electrical attacks applied to the board, including:
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- Reading out of the UDS from the external Flash chip
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- Triggering of the FPGA warm boot functionality
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- Triggering FW update of the CH552 MCU, using the port knocking mechanism
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- Glitching attacks including:
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- Faulting of the execution by the CPU in the FPGA and the CH552 MCU
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- Disturbance of the TRNG entropy generation
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- EM leakage
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#### In scope
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(Attacks we really would like to have investigated.)
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- Digital attacks from the host against the FW in the FPGA, and the FPGA design itself
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via the host interface.
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- Timing attacks on the FW in the FPGA.
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