Joachim Strömbergson 4511096630 FPGA: Add SPI access control logic ... Access logic looks at instruction execution from a defined trampoline address to enable stateful SPI access. The access is disabled as soon as an instruction is executed from any address in RAM. Signed-off-by: Joachim Strömbergson <joachim@assured.se>		2024-08-26 14:09:19 +02:00
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picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
timer	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
tk1	FPGA: Add SPI access control logic	2024-08-26 14:09:19 +02:00
touch_sense	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
trng	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00
uart	FPGA: Increase clock frequency to 21 MHz	2024-08-20 13:45:00 +02:00
uds	Update Verilog version to 2005 for linting	2024-04-24 08:44:08 +02:00