63 lines
2.1 KiB
Markdown
63 lines
2.1 KiB
Markdown
# uds
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Unique Device Secret core
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## Introduction
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This core store and protect the Unique Device Secret (UDS) asset. The
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UDS can be accessed as eight separate 32-bit words. The words can only
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be accessed as long as the fw_app_mode input is low, implying that the
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CPU is executing the FW.
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The UDS words can be accessed in any order, but a given word can only
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be accessed once between reset cycles. This read once functionality is
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implemented with a companion read bit for each word. The read bit is
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set when the word is first accessed. The read bit controls if the real
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UDS word is returned or not.
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This means that the even if the chip select (cs) control
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input is forced high, the content will become all zero when the read
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bit has been set after one cycle.
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## API
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There are eight addresses in the API. These are defined by the
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two values ADDR_UDS_FIRST and ADDR_UDS_LAST:
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```
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ADDR_UDS_FIRST: 0x10
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ADDR_UDS_LAST: 0x17
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```
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These addresses are read only and read once between reset.
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Any access to another address will be ignored by the core.
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## Implementation
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These read-only registers provide read access to the 256-bit UDS.
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The eight UDS words are stored using 32 named SB\_LUT4 FPGA
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multiplexer (MUX) instances, identified in the source code as
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"uds\_rom\_idx". One instance for each bit in the core read\_data
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output bus.
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During build of the FPGA design, the UDS is set to a known bit
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pattern, which means that the SB\_LUT4 instantiations are initialized
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to a fixed bit pattern.
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The tool 'patch\_uds\_udi.py' is used to replace the fixed bit pattern
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with a unique bit pattern before generating the per device unique FPGA
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bitstream. This allows us to generate these device unique FPGA
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bitstreams without haveing to do a full FPGA build.
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Each SB\_LUT4 MUX is able to store 16 bits of data, in total 512 bits.
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But since the UDS is 256 bits, we only use the eight LSBs in each MUX.
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The eighth MSBs in each MUX will be initialized to zero. The read
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access bit (se description above) for a given word is used as the
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highest address bit to the MUXes. This forces any subsequent accesses
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to a UDS word to read from the MUX MSBs, not the LSBs where the UDS is
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stored.
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