Mikael Ågren c98249c3e3 fpga: Experimental fpga build for uwg30 package ... nextpnr-ice40 fails with: ``` Info: Placing PLLs.. ERROR: PLL 'reset_gen_inst.pll_inst' couldn't be placed anywhere, no suitable BEL found. PLL bel 'X12/Y31/pll_3' cannot be used as it conflicts with input 'interface_ch552_cts$sb_io' on pin 'B3'. ```		2025-05-19 08:55:22 +02:00
..
application_fpga_sim.v	fpga: Experimental fpga build for uwg30 package	2025-05-19 08:55:22 +02:00
application_fpga_verilator.cc	fpga: Introduce CTS signals for UART	2025-02-11 13:50:04 +01:00
reset_gen_sim.v	Align module name with its file name.	2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v	fpga: Introduce CTS signals for UART	2025-02-11 13:50:04 +01:00
trng_sim.v	Add verilog file for TRNG simulation	2024-11-28 16:10:00 +01:00