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187 lines
6.1 KiB
Markdown
187 lines
6.1 KiB
Markdown
# The TKey FPGA
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## Introduction
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The TKey application FPGA (application_fpga design) contain
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the application platform CPU system onto which secure applications
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are loaded, measured and executed. The platform is a compact
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System on Chip (SoC) with the following cores.
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The application FPGA is currently implemented using a Lattice
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[iCE40 UltraPlus UP5K device](https://www.latticesemi.com/en/Products/FPGAandCPLD/iCE40UltraPlus).
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Only open tools are used in the toolchain.
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### Top level
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The top level application_fpga design contain instances of all cores as
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well as the memory system. The memory system allows the CPU to access
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cores in different ways given the current exection mode. There are two
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execution modes - firmware and application. Basically, in application mode
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the access is more restrictive.
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The API for all cores is described in the Memory mapped hardware
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functions in the [System
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Description](system_description.md#memory-mapped-hardware-functions).
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### Cores
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#### CPU
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The CPU core is an instance of the [PicoRV32 core](https://github.com/YosysHQ/picorv32).
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The instance enables the following features
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- Compressed ISA (C extension)
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- Fast multiplication. Two cycles for 32x32 multiplication
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- Barrel shifter
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No other modification to the core has been done.
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No interrupts are used.
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#### Clock and reset
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The device does not rely on external clock or reset. Instead the
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internal HFOSC oscillator combined with an internal PLL is used to generate
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the main clock. Currently the clock frequency driving the SoC is 18 MHz.
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The device also generates its own reset.
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#### FW ROM
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The ROM memory containing the firmware. After reset the CPU will
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read from the ROM to load, measure and start applications.
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The RAM memort is only accessible by the firmware.
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#### FW RAM
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A 512w32 small RAM only accessible by the firmware. The firmware
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use the RAM during loading and measurement of the application.
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#### UDS
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Unique Device Secret memory.
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A 256 bit memory implemented using eight 32-bit registers. The
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registers can only be accessed once between power cycling. This means
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that the UDS **must** be read as u32. If read as u8, only the first
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byte from a given address will be correct, subsequent bytes will be
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zero.
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The UDS can only be read in FW mode. Reading from the UDS in APP mode
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will return all zeros.
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#### Application RAM
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The 128 KByte main RAM. The RAM is only used by applications.
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The memory is cleared by firmware before an application is loaded.
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The application RAM is available to use by firmware and applications.
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#### Timer
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A general purpose 32 bit timer. The timer will count down from
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the initial value to one. In order to handle long time sequences
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(minutes, hours, days) there is also a 32 bit prescaler.
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The timer is available to use by firmware and applications.
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#### UART
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A standard UART interface for receiving bytes from and send bytes
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to the host via the interface MCU on the TKey.
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The UART default speed is 62500 bps, but can be adjusted by the
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application. (Note that the host must set the same bitrate too.)
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The UART contain a 512 but Rx-FIFO with status (data available).
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The timer is available to use by firmware and applications.
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#### ROSC
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The ROSC is a ring oscillator based internal entropy source, or
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True Random Number Generator (TRNG). By default the TRNG use 32
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free running digital oscillators. By default, the oscillators are
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sampled after 4096 cycles. The states are XOR combined to create
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a single bit. After another 4096 cycles a second bit is created,
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and the two bits are XOR combined to a single entropy bit. The
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entropy bit is added to a 32 bit entropy word.
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After 32 bits has been collected, the data ready flag is set,
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indicating that an entropy word is ready for consumption. Note
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that entropy bit generation and collections is running continuously,
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bits will be added, and the discarded after 32 more bits have
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been added.
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If a data word has been read from the TRNG, by default at least
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32 bits will collected before new data will be available.
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The ROSC TRNG is available to use by firmware and applications.
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Note: The ROSC generates entropy with a fairly good quality.
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However for security related use cases, for example keys, the ROSC
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should not be used directly. Instead use it to create a seed
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for a Digital Random Bit Generator (DRBG), also known as a
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Cryptographically Safe Pseudo Random Number Generator (CSPRNG).
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Examples of such generators are Hash_DRGG, CTR_DRBG, HKDF.
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#### Touch sensor
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The core provides a stable interface to the touch sensor on the
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TKey device. Using the core, the firmware and applications can
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get information about touch events and manage detection of
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events.
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It is recommended that SW start by acknowledge any stray events prior
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to signal the user that a touch event is expected and then start
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waiting for an event.
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The touch sensor is available to use by firmware and applications.
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#### TKey
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The TKey core contains several functions, and acts as
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main HW interface between firmware and applications. The core
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includes:
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- Read access to the 64 bit FPGA design name, expressed as ASCII chars.
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- Read access to the 32 bit FPGA design version, expressed as an integer
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- Control and status access for the RGB LED on TKey board
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- Setting bit 0 high turns on the Blue LED.
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- Setting bit 1 high turns on the Green LED.
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- Setting bit 2 high turns on the Red LED.
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- Control and status access for the 4 GPIOs on the TKey board
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- GPIO 1 and 2 are inputs and provide read access to the
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current sampled value digital values on the pins.
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- GPIO 3 and 4 are outputs. The digital value written to
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the bits will be presented on the pins.
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- Application read access to information about the loaded
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application. The information is written by the firmware.
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- Start address
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- Size of address
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- Application read access to the CDI generated and written
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by the firmware when the application is loaded.
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- Application-Firmware execution mode control. Can be read
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by the application and written by firmware. When written
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to by the firmware, the hardware will switch to application
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mode and start executing the application.
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