Daniel Jobson 2abe93cf06 Make sensitive assets only readable/writable before system_mode is set ... After the first time system_mode is set to one, the assets will no longer be read- or writeable, even if system_mode is set to zero at a later syscall. This is to make sure syscalls does not have the same privilege as the firmware has at first boot. We need to monitor when system_mode is set to one, otherwise we might accedentially lock the assets before actually leaving firmware, for example if firmware would use a function set in any of the registers used in system_mode_ctrl. Co-authored-by: Mikael Ågren <mikael@tillitis.se>		2024-12-09 13:26:42 +01:00
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clk_reset_gen	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
fw_ram	Doc: fix typo of system mode in readme	2024-11-13 14:13:02 +01:00
picorv32	FPGA: Ignore warnings about blocking assignment in clocked processes	2024-06-17 15:37:13 +02:00
ram	Doc: move implementation details of RAM scrambling to RAM core	2024-11-20 15:48:49 +01:00
rom	Fix typo	2024-11-14 16:35:50 +01:00
timer	tb: make timer core testbench selftesting	2024-11-27 08:10:15 +01:00
tk1	Make sensitive assets only readable/writable before system_mode is set	2024-12-09 13:26:42 +01:00
touch_sense	FPGA: Format verilog code	2024-10-22 12:04:19 +02:00
trng	Change "rosc" references to "trng"	2024-11-14 16:35:51 +01:00
uart	fpga: remove the API for configuring the UART core	2024-11-26 15:24:12 +01:00
uds	Make sensitive assets only readable/writable before system_mode is set	2024-12-09 13:26:42 +01:00