Joachim Strömbergson cc59d8dc93

Update verilator top level module to match rom module changes

2022-10-06 13:59:01 +02:00

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application_fpga_verilator.cc

Update bit divisor calc in verilator's uart to our current 18 MHz

2022-10-03 13:11:53 +02:00

application_fpga_vsim.v

Update verilator top level module to match rom module changes

2022-10-06 13:59:01 +02:00

reset_gen_vsim.v

Fix Verilator sim by adding separate reset generator

2022-10-03 12:55:24 +02:00