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tillitis-key/hw/application_fpga/tb
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Mikael Ågren 19ae709c81
fpga: Add syscall interrupt 
Add syscall interrupt to be used for syscalls. The interrupt is
triggered by writing to an address in the 0xe1000000-0xe1ffffff

The PicoRV32 core is configured to use its minimal, non RISCV-standard,
interrupt implementation.
2025-02-27 14:20:28 +01:00
..
application_fpga_sim.v
fpga: Add syscall interrupt
2025-02-27 14:20:28 +01:00
application_fpga_verilator.cc
fpga: Introduce CTS signals for UART
2025-02-11 13:50:04 +01:00
reset_gen_sim.v
Align module name with its file name.
2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v
fpga: Introduce CTS signals for UART
2025-02-11 13:50:04 +01:00
trng_sim.v
Add verilog file for TRNG simulation
2024-11-28 16:10:00 +01:00