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tillitis-key/hw/application_fpga/tb
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Jonas Thörnblad ede92af2c1
Updated application_fpga_verilator.cc to match module application_fpga_sim. 
- include printout of used clock and baud rate speed
- Use the the same clock frequency as target
2024-11-28 16:10:01 +01:00
..
application_fpga_sim.v
Set APP_SIZE if not defined.
2024-11-28 16:10:01 +01:00
application_fpga_verilator.cc
Updated application_fpga_verilator.cc to match module application_fpga_sim.
2024-11-28 16:10:01 +01:00
reset_gen_sim.v
Align module name with its file name.
2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v
Add top level testbench for application_fpga_sim.v
2024-11-28 16:10:00 +01:00
trng_sim.v
Add verilog file for TRNG simulation
2024-11-28 16:10:00 +01:00