Daniel Jobson 2abe93cf06 Make sensitive assets only readable/writable before system_mode is set ... After the first time system_mode is set to one, the assets will no longer be read- or writeable, even if system_mode is set to zero at a later syscall. This is to make sure syscalls does not have the same privilege as the firmware has at first boot. We need to monitor when system_mode is set to one, otherwise we might accedentially lock the assets before actually leaving firmware, for example if firmware would use a function set in any of the registers used in system_mode_ctrl. Co-authored-by: Mikael Ågren <mikael@tillitis.se>		2024-12-09 13:26:42 +01:00
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application_fpga_sim.v	Make sensitive assets only readable/writable before system_mode is set	2024-12-09 13:26:42 +01:00
application_fpga_verilator.cc	Updated application_fpga_verilator.cc to match module application_fpga_sim.	2024-11-28 16:10:01 +01:00
reset_gen_sim.v	Align module name with its file name.	2024-11-28 16:09:59 +01:00
tb_application_fpga_sim.v	Add top level testbench for application_fpga_sim.v	2024-11-28 16:10:00 +01:00
trng_sim.v	Add verilog file for TRNG simulation	2024-11-28 16:10:00 +01:00