diff --git a/hw/application_fpga/core/tk1/rtl/tk1.v b/hw/application_fpga/core/tk1/rtl/tk1.v
index 488316c..4e22ce1 100644
--- a/hw/application_fpga/core/tk1/rtl/tk1.v
+++ b/hw/application_fpga/core/tk1/rtl/tk1.v
@@ -26,7 +26,7 @@ module tk1(
 	   output wire          force_trap,
 	   output               system_reset,
 
-	   output wire [31 : 0] syscall_addr,
+	   output wire [31 : 0] syscall_instr,
 	   output wire          syscall,
 
 	   output wire [14 : 0] ram_addr_rand,
@@ -84,7 +84,7 @@ module tk1(
 
   localparam ADDR_BLAKE2S       = 8'h10;
 
-  localparam ADDR_SYSCALL_ADDR  = 8'h12;
+  localparam ADDR_SYSCALL_INSTR = 8'h12;
   localparam ADDR_SYSCALL_START = 8'h13;
 
   localparam ADDR_CDI_FIRST     = 8'h20;
@@ -144,8 +144,11 @@ module tk1(
   reg [31 : 0] blake2s_addr_reg;
   reg          blake2s_addr_we;
 
-  reg [31 : 0] syscall_addr_reg;
-  reg          syscall_addr_we;
+  reg [31 : 0] syscall_instr_reg;
+  reg          syscall_instr_we;
+
+  reg          syscall_reg;
+  reg          syscall_new;
 
   reg [23 : 0] cpu_trap_ctr_reg;
   reg [23 : 0] cpu_trap_ctr_new;
@@ -215,8 +218,8 @@ module tk1(
 
   assign system_reset = system_reset_reg;
 
-  assign syscall_addr = syscall_addr_reg;
-  assign syscall      = start_syscall;
+  assign syscall_instr = syscall_instr_reg;
+  assign syscall      = syscall_reg;
 
 
   //----------------------------------------------------------------
@@ -282,7 +285,8 @@ module tk1(
         app_start_reg     <= 32'h0;
         app_size_reg      <= 32'h0;
         blake2s_addr_reg  <= 32'h0;
-        syscall_addr_reg  <= 32'h0;
+        syscall_instr_reg <= 32'h0;
+	syscall_reg       <= 1'h0;
 	cdi_mem[0]        <= 32'h0;
 	cdi_mem[1]        <= 32'h0;
 	cdi_mem[2]        <= 32'h0;
@@ -306,6 +310,7 @@ module tk1(
 	cpu_trap_ctr_reg <= cpu_trap_ctr_new;
 
 	system_reset_reg <= system_reset_new;
+	syscall_reg <= syscall_new;
 
         gpio1_reg[0] <= gpio1;
         gpio1_reg[1] <= gpio1_reg[0];
@@ -341,8 +346,8 @@ module tk1(
           blake2s_addr_reg <= write_data;
         end
 
-        if (syscall_addr_we) begin
-          syscall_addr_reg <= write_data;
+        if (syscall_instr_we) begin
+          syscall_instr_reg <= write_data;
         end
 
 	if (cdi_mem_we) begin
@@ -455,8 +460,8 @@ module tk1(
       app_start_we     = 1'h0;
       app_size_we      = 1'h0;
       blake2s_addr_we  = 1'h0;
-      syscall_addr_we  = 1'h0;
-      start_syscall    = 1'h0;
+      syscall_instr_we = 1'h0;
+      syscall_new      = 1'h0;
       cdi_mem_we       = 1'h0;
       cdi_mem_we       = 1'h0;
       ram_addr_rand_we = 1'h0;
@@ -516,14 +521,14 @@ module tk1(
             end
 	  end
 
-          if (address == ADDR_SYSCALL_ADDR) begin
+          if (address == ADDR_SYSCALL_INSTR) begin
 	    if (!switch_app_reg) begin
-              syscall_addr_we = 1'h1;
+              syscall_instr_we = 1'h1;
             end
 	  end
 
           if (address == ADDR_SYSCALL_START) begin
-            start_syscall = 1'h1;
+            syscall_new = 1'h1;
 	  end
 
 	  if ((address >= ADDR_CDI_FIRST) && (address <= ADDR_CDI_LAST)) begin
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index c783cac..06b633a 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -149,7 +149,7 @@ module application_fpga(
   wire [14 : 0] ram_addr_rand;
   wire [31 : 0] ram_data_rand;
   wire          tk1_system_reset;
-  wire [31 : 0] tk1_syscall_addr;
+  wire [31 : 0] tk1_syscall_instr;
   wire          tk1_syscall;
   /* verilator lint_on UNOPTFLAT */
 
@@ -330,7 +330,7 @@ module application_fpga(
 
 	       .system_reset(tk1_system_reset),
 
-	       .syscall_addr(tk1_syscall_addr),
+	       .syscall_instr(tk1_syscall_instr),
 	       .syscall(tk1_syscall),
 
                .ram_addr_rand(ram_addr_rand),
@@ -439,6 +439,12 @@ module application_fpga(
 	  muxed_rdata_new = ILLEGAL_INSTRUCTION;
 	  muxed_ready_new = 1'h1;
 	end
+
+	else if (tk1_syscall) begin
+	  muxed_rdata_new = tk1_syscall_instr;
+	  muxed_ready_new = 1'h1;
+	end
+
 	else begin
           case (area_prefix)
             ROM_PREFIX: begin
@@ -448,16 +454,10 @@ module application_fpga(
             end
 
             RAM_PREFIX: begin
-	      if (tk1_syscall) begin
-		muxed_rdata_new = tk1_syscall_addr;
-		muxed_ready_new = 1'h1;
-	      end
-	      else begin
-		ram_cs          = 1'h1;
-		ram_we          = cpu_wstrb;
-		muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
-		muxed_ready_new = ram_ready;
-	      end
+	      ram_cs          = 1'h1;
+	      ram_we          = cpu_wstrb;
+	      muxed_rdata_new = ram_read_data ^ ram_data_rand ^ {2{cpu_addr[15 : 0]}};
+	      muxed_ready_new = ram_ready;
 	    end
 
             RESERVED_PREFIX: begin