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Update bit counter to match 18 MHz clock frequency

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Joachim Strömbergson 2022-09-30 10:04:37 +02:00
parent 90a57c4948
commit f41573cc60
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GPG Key ID: 865B8A548EA61679
1 changed files with 3 additions and 3 deletions
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hw/application_fpga/core/uart/rtl/uart.v
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@ -90,9 +90,9 @@ module uart(
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 12 MHz, 38400 bps
// Divisor = 12*10E6 / 38400 = 312
localparam DEFAULT_BIT_RATE = 16'd312;
// Clock: 18 MHz, 38400 bps
// Divisor = 18*10E6 / 38400 = 468.75 ~ 469
localparam DEFAULT_BIT_RATE = 16'd469;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;