From f41573cc600e32310493702983b8fe8f416b1626 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 30 Sep 2022 10:04:37 +0200 Subject: [PATCH] Update bit counter to match 18 MHz clock frequency --- hw/application_fpga/core/uart/rtl/uart.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart.v b/hw/application_fpga/core/uart/rtl/uart.v index 092ec4c..729418d 100644 --- a/hw/application_fpga/core/uart/rtl/uart.v +++ b/hw/application_fpga/core/uart/rtl/uart.v @@ -90,9 +90,9 @@ module uart( // The default bit rate is based on target clock frequency // divided by the bit rate times in order to hit the // center of the bits. I.e. - // Clock: 12 MHz, 38400 bps - // Divisor = 12*10E6 / 38400 = 312 - localparam DEFAULT_BIT_RATE = 16'd312; + // Clock: 18 MHz, 38400 bps + // Divisor = 18*10E6 / 38400 = 468.75 ~ 469 + localparam DEFAULT_BIT_RATE = 16'd469; localparam DEFAULT_DATA_BITS = 4'h8; localparam DEFAULT_STOP_BITS = 2'h1;