Git-Mirrors/tillitis-key
1
0
Fork 0
mirror of https://github.com/tillitis/tillitis-key1.git synced 2025-06-06 21:48:52 -04:00
Code Issues Projects Releases Packages Wiki Activity

Implement cs0 and cs1 as logic equations, not muxes

Browse source 
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2024-03-18 14:41:52 +01:00 • committed by Michael Cardell Widerkrantz
parent 0590445f3d
commit e48c0fc7d9
No known key found for this signature in database
GPG key ID: D3DB3DDF57E704E5
1 changed files with 2 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

6
hw/application_fpga/rtl/ram.v
View file

@ -125,14 +125,12 @@ module ram(
//---------------------------------------------------------------- //----------------------------------------------------------------
always @* always @*
begin : mem_mux begin : mem_mux
cs0 = 1'h0; cs0 = ~address[14] & cs;
cs1 = 1'h0; cs1 = address[14] & cs;
if (address[14]) begin if (address[14]) begin
cs1 = cs;
muxed_read_data = read_data1; muxed_read_data = read_data1;
end else begin end else begin
cs0 = cs;
muxed_read_data = read_data0; muxed_read_data = read_data0;
end end
end end