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Align module name with its file name.

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Jonas Thörnblad 2024-11-25 15:01:34 +01:00 committed by Daniel Jobson
parent e54045a4dd
commit d3b9660180
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1 changed files with 5 additions and 5 deletions
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hw/application_fpga/tb/reset_gen_sim.v
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@ -1,8 +1,8 @@
//====================================================================== //======================================================================
// //
// reset_gen_sim.v // reset_gen_sim.v
// ---------------- // ---------------
// Reset generator Verilator simulation of the application_fpga. // Reset generator simulation of the application_fpga.
// //
// //
// Author: Joachim Strombergson // Author: Joachim Strombergson
@ -13,7 +13,7 @@
`default_nettype none `default_nettype none
module reset_gen #( module reset_gen_sim #(
parameter RESET_CYCLES = 200 parameter RESET_CYCLES = 200
) ( ) (
input wire clk, input wire clk,
@ -63,8 +63,8 @@ module reset_gen #(
end end
end end
endmodule // reset_gen endmodule // reset_gen_sim
//====================================================================== //======================================================================
// EOF reset_gen.v // EOF reset_gen_sim.v
//====================================================================== //======================================================================