From d3b9660180b9d3f689df7b650a475df66bfb6431 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Th=C3=B6rnblad?= Date: Mon, 25 Nov 2024 15:01:34 +0100 Subject: [PATCH] Align module name with its file name. --- hw/application_fpga/tb/reset_gen_sim.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/application_fpga/tb/reset_gen_sim.v b/hw/application_fpga/tb/reset_gen_sim.v index 6187d4c..de573d6 100644 --- a/hw/application_fpga/tb/reset_gen_sim.v +++ b/hw/application_fpga/tb/reset_gen_sim.v @@ -1,8 +1,8 @@ //====================================================================== // // reset_gen_sim.v -// ---------------- -// Reset generator Verilator simulation of the application_fpga. +// --------------- +// Reset generator simulation of the application_fpga. // // // Author: Joachim Strombergson @@ -13,7 +13,7 @@ `default_nettype none -module reset_gen #( +module reset_gen_sim #( parameter RESET_CYCLES = 200 ) ( input wire clk, @@ -63,8 +63,8 @@ module reset_gen #( end end -endmodule // reset_gen +endmodule // reset_gen_sim //====================================================================== -// EOF reset_gen.v +// EOF reset_gen_sim.v //======================================================================