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Add HW to detect trap in cpu and signal using the LEDs

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson 2023-02-27 13:05:24 +01:00
parent e04b502833
commit d335dd708a
2 changed files with 47 additions and 4 deletions
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4
hw/application_fpga/rtl/application_fpga.v
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@ -68,6 +68,7 @@ module application_fpga(
wire clk;
wire reset_n;
wire cpu_trap;
wire cpu_valid;
wire [03 : 0] cpu_wstrb;
/* verilator lint_off UNUSED */
@ -168,6 +169,7 @@ module application_fpga(
) cpu(
.clk(clk),
.resetn(reset_n),
.trap(cpu_trap),
.mem_valid(cpu_valid),
.mem_ready(muxed_ready_reg),
@ -181,7 +183,6 @@ module application_fpga(
/* verilator lint_off PINCONNECTEMPTY */
.irq(32'h0),
.eoi(),
.trap(),
.trace_valid(),
.trace_data(),
.mem_instr(),
@ -310,6 +311,7 @@ module application_fpga(
.clk(clk),
.reset_n(reset_n),
.cpu_trap(cpu_trap),
.fw_app_mode(fw_app_mode),
.led_r(led_r),