From d335dd708a529c6b311aedac48bd5e986070e025 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Mon, 27 Feb 2023 13:05:24 +0100 Subject: [PATCH] Add HW to detect trap in cpu and signal using the LEDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/core/tk1/rtl/tk1.v | 47 ++++++++++++++++++++-- hw/application_fpga/rtl/application_fpga.v | 4 +- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/hw/application_fpga/core/tk1/rtl/tk1.v b/hw/application_fpga/core/tk1/rtl/tk1.v index 4142192..b406bde 100644 --- a/hw/application_fpga/core/tk1/rtl/tk1.v +++ b/hw/application_fpga/core/tk1/rtl/tk1.v @@ -17,6 +17,7 @@ module tk1( input wire clk, input wire reset_n, + input wire cpu_trap, output wire fw_app_mode, output wire led_r, @@ -103,8 +104,15 @@ module tk1( reg app_size_we; reg [31 : 0] blake2s_addr_reg; + reg [31 : 0] blake2s_addr_new; reg blake2s_addr_we; + reg [23 : 0] cpu_trap_ctr_reg; + reg [23 : 0] cpu_trap_ctr_new; + reg [2 : 0] cpu_trap_led_reg; + reg [2 : 0] cpu_trap_led_new; + reg cpu_trap_led_we; + //---------------------------------------------------------------- // Wires. @@ -114,6 +122,8 @@ module tk1( reg tmp_ready; /* verilator lint_on UNOPTFLAT */ + reg [2 : 0] muxed_led; + //---------------------------------------------------------------- // Concurrent connectivity for ports etc. @@ -141,9 +151,9 @@ module tk1( .RGB1(led_g), .RGB2(led_b), .RGBLEDEN(1'h1), - .RGB0PWM(led_reg[LED_R_BIT]), - .RGB1PWM(led_reg[LED_G_BIT]), - .RGB2PWM(led_reg[LED_B_BIT]), + .RGB0PWM(muxed_led[LED_R_BIT]), + .RGB1PWM(muxed_led[LED_G_BIT]), + .RGB2PWM(muxed_led[LED_B_BIT]), .CURREN(1'b1) ); /* verilator lint_on PINMISSING */ @@ -172,9 +182,13 @@ module tk1( cdi_mem[5] <= 32'h0; cdi_mem[6] <= 32'h0; cdi_mem[7] <= 32'h0; + cpu_trap_ctr_reg <= 24'h0; + cpu_trap_led_reg <= 3'h4; end else begin + cpu_trap_ctr_reg <= cpu_trap_ctr_new; + gpio1_reg[0] <= gpio1; gpio1_reg[1] <= gpio1_reg[0]; @@ -212,10 +226,37 @@ module tk1( if (cdi_mem_we) begin cdi_mem[address[2 : 0]] <= write_data; end + + if (cpu_trap_led_we) begin + cpu_trap_led_reg <= cpu_trap_led_new; + end end end // reg_update + //---------------------------------------------------------------- + // trap_led_logic + //---------------------------------------------------------------- + always @* + begin : trap_led_logic + cpu_trap_led_new = 3'h0; + cpu_trap_led_we = 1'h0; + + cpu_trap_ctr_new = cpu_trap_ctr_reg + 1'h1; + + if (cpu_trap_ctr_reg == 24'h0) begin + cpu_trap_led_new = cpu_trap_led_reg ^ 3'h4; + cpu_trap_led_we = 1'h1; + end + + if (cpu_trap) begin + muxed_led = cpu_trap_led_reg; + end else begin + muxed_led = led_reg; + end + end + + //---------------------------------------------------------------- // api //---------------------------------------------------------------- diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v index 2fde3b1..43fa663 100644 --- a/hw/application_fpga/rtl/application_fpga.v +++ b/hw/application_fpga/rtl/application_fpga.v @@ -68,6 +68,7 @@ module application_fpga( wire clk; wire reset_n; + wire cpu_trap; wire cpu_valid; wire [03 : 0] cpu_wstrb; /* verilator lint_off UNUSED */ @@ -168,6 +169,7 @@ module application_fpga( ) cpu( .clk(clk), .resetn(reset_n), + .trap(cpu_trap), .mem_valid(cpu_valid), .mem_ready(muxed_ready_reg), @@ -181,7 +183,6 @@ module application_fpga( /* verilator lint_off PINCONNECTEMPTY */ .irq(32'h0), .eoi(), - .trap(), .trace_valid(), .trace_data(), .mem_instr(), @@ -310,6 +311,7 @@ module application_fpga( .clk(clk), .reset_n(reset_n), + .cpu_trap(cpu_trap), .fw_app_mode(fw_app_mode), .led_r(led_r),