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FPGA: Move all sub modules into separate cores

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-08-20 10:50:26 +02:00 committed by Daniel Jobson
parent b8f22a9810
commit d1cff273d7
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GPG Key ID: 3707A9DBF4BB8F1A
5 changed files with 4 additions and 4 deletions
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8
hw/application_fpga/Makefile
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@ -54,7 +54,7 @@ ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v)
# FPGA specific source files. # FPGA specific source files.
FPGA_SRC = $(P)/rtl/application_fpga.v \ FPGA_SRC = $(P)/rtl/application_fpga.v \
$(P)/rtl/clk_reset_gen.v $(P)/core/clk_reset_gen/rtl/clk_reset_gen.v
# Verilator simulation specific source files. # Verilator simulation specific source files.
VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \ VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
@ -62,9 +62,9 @@ VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \
# Common verilog source files. # Common verilog source files.
VERILOG_SRCS = \ VERILOG_SRCS = \
$(P)/rtl/ram.v \ $(P)/core/ram/rtl/ram.v \
$(P)/rtl/rom.v \ $(P)/core/rom/rtl/rom.v \
$(P)/rtl/fw_ram.v \ $(P)/core/fw_ram/rtl/fw_ram.v \
$(P)/core/picorv32/rtl/picorv32.v \ $(P)/core/picorv32/rtl/picorv32.v \
$(P)/core/timer/rtl/timer_core.v \ $(P)/core/timer/rtl/timer_core.v \
$(P)/core/timer/rtl/timer.v \ $(P)/core/timer/rtl/timer.v \

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hw/application_fpga/rtl/clk_reset_gen.v → hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v
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hw/application_fpga/rtl/fw_ram.v → hw/application_fpga/core/fw_ram/rtl/fw_ram.v
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hw/application_fpga/rtl/ram.v → hw/application_fpga/core/ram/rtl/ram.v
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hw/application_fpga/rtl/rom.v → hw/application_fpga/core/rom/rtl/rom.v
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