From d1cff273d78b87235eee7f72a79f4dec8daab5dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 20 Aug 2024 10:50:26 +0200 Subject: [PATCH] FPGA: Move all sub modules into separate cores MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- hw/application_fpga/Makefile | 8 ++++---- .../{ => core/clk_reset_gen}/rtl/clk_reset_gen.v | 0 hw/application_fpga/{ => core/fw_ram}/rtl/fw_ram.v | 0 hw/application_fpga/{ => core/ram}/rtl/ram.v | 0 hw/application_fpga/{ => core/rom}/rtl/rom.v | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename hw/application_fpga/{ => core/clk_reset_gen}/rtl/clk_reset_gen.v (100%) rename hw/application_fpga/{ => core/fw_ram}/rtl/fw_ram.v (100%) rename hw/application_fpga/{ => core/ram}/rtl/ram.v (100%) rename hw/application_fpga/{ => core/rom}/rtl/rom.v (100%) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 4653480..9906750 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -54,7 +54,7 @@ ICE40_SIM_CELLS = $(shell yosys-config --datdir/ice40/cells_sim.v) # FPGA specific source files. FPGA_SRC = $(P)/rtl/application_fpga.v \ - $(P)/rtl/clk_reset_gen.v + $(P)/core/clk_reset_gen/rtl/clk_reset_gen.v # Verilator simulation specific source files. VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \ @@ -62,9 +62,9 @@ VERILATOR_FPGA_SRC = $(P)/tb/application_fpga_vsim.v \ # Common verilog source files. VERILOG_SRCS = \ - $(P)/rtl/ram.v \ - $(P)/rtl/rom.v \ - $(P)/rtl/fw_ram.v \ + $(P)/core/ram/rtl/ram.v \ + $(P)/core/rom/rtl/rom.v \ + $(P)/core/fw_ram/rtl/fw_ram.v \ $(P)/core/picorv32/rtl/picorv32.v \ $(P)/core/timer/rtl/timer_core.v \ $(P)/core/timer/rtl/timer.v \ diff --git a/hw/application_fpga/rtl/clk_reset_gen.v b/hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v similarity index 100% rename from hw/application_fpga/rtl/clk_reset_gen.v rename to hw/application_fpga/core/clk_reset_gen/rtl/clk_reset_gen.v diff --git a/hw/application_fpga/rtl/fw_ram.v b/hw/application_fpga/core/fw_ram/rtl/fw_ram.v similarity index 100% rename from hw/application_fpga/rtl/fw_ram.v rename to hw/application_fpga/core/fw_ram/rtl/fw_ram.v diff --git a/hw/application_fpga/rtl/ram.v b/hw/application_fpga/core/ram/rtl/ram.v similarity index 100% rename from hw/application_fpga/rtl/ram.v rename to hw/application_fpga/core/ram/rtl/ram.v diff --git a/hw/application_fpga/rtl/rom.v b/hw/application_fpga/core/rom/rtl/rom.v similarity index 100% rename from hw/application_fpga/rtl/rom.v rename to hw/application_fpga/core/rom/rtl/rom.v