mirror of
https://github.com/tillitis/tillitis-key1.git
synced 2025-05-02 06:06:24 -04:00
FPGA: Move all sub modules into separate cores
Signed-off-by: Joachim Strömbergson <joachim@assured.se>
This commit is contained in:
Joachim Strömbergson
Daniel Jobson
parent
b8f22a9810
commit
d1cff273d7
5 changed files with 4 additions and 4 deletions
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@ -1,137 +0,0 @@
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//======================================================================
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//
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// clk_reset_gen.v
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// -----------
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// Clock and reset generator used in the Tillitis Key 1 design.
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// This module instantiate the internal SB_HFOSC clock source in the
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// Lattice ice40 UP device. It then connects it to the PLL, and
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// finally connects the output from the PLL to the global clock net.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module clk_reset_gen #(parameter RESET_CYCLES = 200)
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(
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input wire sys_reset,
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output wire clk,
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output wire rst_n
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);
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//----------------------------------------------------------------
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// Registers with associated wires.
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//----------------------------------------------------------------
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reg [7 : 0] rst_ctr_reg = 8'h0;
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reg [7 : 0] rst_ctr_new;
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reg rst_ctr_we;
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reg rst_n_reg = 1'h0;
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reg rst_n_new;
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reg sys_reset_reg;
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//----------------------------------------------------------------
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// Wires.
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//----------------------------------------------------------------
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wire hfosc_clk;
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wire pll_clk;
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//----------------------------------------------------------------
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// Concurrent assignment.
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//----------------------------------------------------------------
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assign rst_n = rst_n_reg;
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//----------------------------------------------------------------
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// Core instantiations.
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//----------------------------------------------------------------
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/* verilator lint_off PINMISSING */
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// Use the FPGA internal High Frequency OSCillator as clock source.
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// 00: 48MHz, 01: 24MHz, 10: 12MHz, 11: 6MHz
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SB_HFOSC #(.CLKHF_DIV("0b10")
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) hfosc_inst (.CLKHFPU(1'b1),.CLKHFEN(1'b1),.CLKHF(hfosc_clk));
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// Use a PLL to generate a new clock frequency based on the HFOSC clock.
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//
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// Given FEEDBACK_PATH=="SIMPLE", clock calculation according to 3.5.2 in
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// FPGA-TN-02052-1-4-iCE40-sysCLOCK-PLL-Design-User-Guide.pdf
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// https://www.latticesemi.com/view_document?document_id=47778 follows:
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//
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// F_pllout == (F_referenceclk * (DIVF + 1)) / (2^DIVQ * (DIVR + 1))
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//
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// Given the 12 MHz HFOSC clock set above, we get a final 21 MHz:
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//
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// (12000000 * (55 + 1)) / (2^5 * (0 + 1)) = 21000000
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0), // DIVR = 0
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.DIVF(7'd55), // DIVF = 55
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.DIVQ(3'd5), // DIVQ = 5
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.FILTER_RANGE(3'b001) // FILTER_RANGE = 1
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) pll_inst (
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.REFERENCECLK(hfosc_clk),
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.PLLOUTCORE(pll_clk)
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);
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// Use a Global Buffer to distribute the clock.
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SB_GB gb_inst (
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.USER_SIGNAL_TO_GLOBAL_BUFFER (pll_clk),
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.GLOBAL_BUFFER_OUTPUT (clk)
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);
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/* verilator lint_on PINMISSING */
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//----------------------------------------------------------------
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// reg_update.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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rst_n_reg <= rst_n_new;
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sys_reset_reg <= sys_reset;
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if (rst_ctr_we)
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rst_ctr_reg <= rst_ctr_new;
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end
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//----------------------------------------------------------------
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// rst_logic.
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//----------------------------------------------------------------
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always @*
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begin : rst_logic
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rst_n_new = 1'h1;
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h0;
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if (sys_reset_reg) begin
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rst_ctr_new = 8'h0;
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rst_ctr_we = 1'h1;
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end
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else if (rst_ctr_reg < RESET_CYCLES) begin
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rst_n_new = 1'h0;
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rst_ctr_new = rst_ctr_reg + 1'h1;
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rst_ctr_we = 1'h1;
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end
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end
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endmodule // reset_gen
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//======================================================================
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// EOF reset_gen.v
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//======================================================================
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@ -1,150 +0,0 @@
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//======================================================================
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//
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// fw_ram.v
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// --------
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// A 512 x 32 RAM (2048 bytes) for use by the FW. The memory has
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// support for mode based access control.
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module fw_ram(
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input wire clk,
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input wire reset_n,
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input wire fw_app_mode,
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input wire cs,
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input wire [3 : 0] we,
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input wire [8 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg [31 : 0] tmp_read_data;
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reg [31 : 0] mem_read_data0;
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reg [31 : 0] mem_read_data1;
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reg ready_reg;
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wire fw_app_cs;
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reg bank0;
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reg bank1;
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//----------------------------------------------------------------
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// Concurrent assignment of ports.
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//----------------------------------------------------------------
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assign read_data = tmp_read_data;
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assign ready = ready_reg;
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assign fw_app_cs = cs && ~fw_app_mode;
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//----------------------------------------------------------------
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// Block RAM instances.
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//----------------------------------------------------------------
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SB_RAM40_4K fw_ram0_0(
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.RDATA(mem_read_data0[15 : 0]),
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.RADDR({3'h0, address[7 : 0]}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs & bank0),
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.WADDR({3'h0, address[7 : 0]}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[15 : 0]),
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.WE((|we & fw_app_cs & bank0)),
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.MASK({{8{~we[1]}}, {8{~we[0]}}})
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);
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SB_RAM40_4K fw_ram0_1(
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.RDATA(mem_read_data0[31 : 16]),
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.RADDR({3'h0, address[7 : 0]}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs & bank0),
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.WADDR({3'h0, address[7 : 0]}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[31 : 16]),
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.WE((|we & fw_app_cs & bank0)),
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.MASK({{8{~we[3]}}, {8{~we[2]}}})
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);
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SB_RAM40_4K fw_ram1_0(
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.RDATA(mem_read_data1[15 : 0]),
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.RADDR({3'h0, address[7 : 0]}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs & bank1),
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.WADDR({3'h0, address[7 : 0]}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[15 : 0]),
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.WE((|we & fw_app_cs & bank1)),
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.MASK({{8{~we[1]}}, {8{~we[0]}}})
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);
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SB_RAM40_4K fw_ram1_1(
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.RDATA(mem_read_data1[31 : 16]),
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.RADDR({3'h0, address[7 : 0]}),
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.RCLK(clk),
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.RCLKE(1'h1),
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.RE(fw_app_cs & bank1),
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.WADDR({3'h0, address[7 : 0]}),
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.WCLK(clk),
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.WCLKE(1'h1),
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.WDATA(write_data[31 : 16]),
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.WE((|we & fw_app_cs & bank1)),
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.MASK({{8{~we[3]}}, {8{~we[2]}}})
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);
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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//----------------------------------------------------------------
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// rw_mux
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//----------------------------------------------------------------
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always @*
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begin : rw_mux;
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bank0 = 1'h0;
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bank1 = 1'h0;
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tmp_read_data = 32'h0;
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if (fw_app_cs) begin
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if (address[8]) begin
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bank1 = 1'h1;
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tmp_read_data = mem_read_data1;
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end
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else begin
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bank0 = 1'h1;
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tmp_read_data = mem_read_data0;
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end
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end
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end
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endmodule // fw_ram
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//======================================================================
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// EOF fw_ram.v
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//======================================================================
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@ -1,142 +0,0 @@
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//======================================================================
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//
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// ram.v
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// -----
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// Module that encapsulates the four SPRAM blocks in the Lattice
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// iCE40UP 5K device. This creates a single 32-bit wide,
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// 128 kByte large memory.
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module ram(
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input wire clk,
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input wire reset_n,
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input wire cs,
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input wire [03 : 0] we,
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input wire [14 : 0] address,
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input wire [31 : 0] write_data,
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers and wires.
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//----------------------------------------------------------------
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reg ready_reg;
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reg cs0;
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reg cs1;
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reg [31 : 0] read_data0;
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reg [31 : 0] read_data1;
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reg [31 : 0] muxed_read_data;
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//----------------------------------------------------------------
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// Concurrent assignment of ports.
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//----------------------------------------------------------------
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assign read_data = muxed_read_data;
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assign ready = ready_reg;
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//----------------------------------------------------------------
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// SPRAM instances.
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//----------------------------------------------------------------
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SB_SPRAM256KA spram0(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[15:0]),
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.MASKWREN({we[1], we[1], we[0], we[0]}),
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.WREN(we[1] | we[0]),
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.CHIPSELECT(cs0),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data0[15:0])
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);
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SB_SPRAM256KA spram1(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[31:16]),
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.MASKWREN({we[3], we[3], we[2], we[2]}),
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.WREN(we[3] | we[2]),
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.CHIPSELECT(cs0),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data0[31:16])
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);
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SB_SPRAM256KA spram2(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[15:0]),
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.MASKWREN({we[1], we[1], we[0], we[0]}),
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.WREN(we[1] | we[0]),
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.CHIPSELECT(cs1),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data1[15:0])
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);
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SB_SPRAM256KA spram3(
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.ADDRESS(address[13:0]),
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.DATAIN(write_data[31:16]),
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.MASKWREN({we[3], we[3], we[2], we[2]}),
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.WREN(we[3] | we[2]),
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.CHIPSELECT(cs1),
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.CLOCK(clk),
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.STANDBY(1'b0),
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.SLEEP(1'b0),
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.POWEROFF(1'b1),
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.DATAOUT(read_data1[31:16])
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);
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//----------------------------------------------------------------
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// reg_update
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//
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// Posedge triggered with synchronous, active low reset.
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// This simply creates a one cycle access latency to match
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// the latency of the spram blocks.
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//----------------------------------------------------------------
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always @(posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end
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//----------------------------------------------------------------
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// mem_mux
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//----------------------------------------------------------------
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always @*
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begin : mem_mux
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cs0 = ~address[14] & cs;
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cs1 = address[14] & cs;
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if (address[14]) begin
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muxed_read_data = read_data1;
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end else begin
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muxed_read_data = read_data0;
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end
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end
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endmodule // ram
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//======================================================================
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// EOF ram.v
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//======================================================================
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@ -1,86 +0,0 @@
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//======================================================================
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//
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// rom..v
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// ------
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// Firmware ROM module. Implemented using Embedded Block RAM
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// in the FPGA.
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//
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//
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// Author: Joachim Strombergson
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// Copyright (C) 2022 - Tillitis AB
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// SPDX-License-Identifier: GPL-2.0-only
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//
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//======================================================================
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`default_nettype none
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module rom(
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input wire clk,
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input wire reset_n,
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input wire cs,
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/* verilator lint_off UNUSED */
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input wire [11 : 0] address,
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/* verilator lint_on UNUSED */
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output wire [31 : 0] read_data,
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output wire ready
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);
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//----------------------------------------------------------------
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// Registers, memories with associated wires.
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//----------------------------------------------------------------
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// Size of the sysMem Embedded Block RAM (EBR) memory primarily
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// used for code storage (ROM). The size is number of
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// 32-bit words. Each EBR is 4kbit in size, and (at most)
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// 16-bit wide. Thus means that we use pairs of EBRs, and
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// each pair store 256 32bit words.
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// The size of the EBR allocated to memory must match the
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// size of the firmware file generated by the Makefile.
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//
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// Max size for the ROM is 3072 words, and the address is
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// 12 bits to support ROM with this number of words.
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localparam EBR_MEM_SIZE = `BRAM_FW_SIZE;
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reg [31 : 0] memory [0 : (EBR_MEM_SIZE - 1)];
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initial $readmemh(`FIRMWARE_HEX, memory);
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reg [31 : 0] rom_rdata;
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reg ready_reg;
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//----------------------------------------------------------------
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// Concurrent assignments of ports.
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//----------------------------------------------------------------
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assign read_data = rom_rdata;
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assign ready = ready_reg;
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//----------------------------------------------------------------
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// reg_update
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//----------------------------------------------------------------
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always @ (posedge clk)
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begin : reg_update
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if (!reset_n) begin
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ready_reg <= 1'h0;
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end
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else begin
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ready_reg <= cs;
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end
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end // reg_update
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//----------------------------------------------------------------
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// rom_logic
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//----------------------------------------------------------------
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always @*
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begin : rom_logic
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/* verilator lint_off WIDTH */
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rom_rdata = memory[address];
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/* verilator lint_on WIDTH */
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end
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endmodule // rom
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//======================================================================
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// EOF rom..v
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//======================================================================
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