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Update verilator top level module to match rom module changes

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Joachim Strömbergson 2022-10-06 13:59:01 +02:00
parent f80aaa4e8a
commit cc59d8dc93
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1 changed files with 0 additions and 3 deletions
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hw/application_fpga/tb/application_fpga_vsim.v
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@ -222,9 +222,6 @@ module application_fpga(
rom rom_inst( rom rom_inst(
.clk(clk),
.reset_n(reset_n),
.cs(rom_cs), .cs(rom_cs),
.address(rom_address), .address(rom_address),
.read_data(rom_read_data), .read_data(rom_read_data),