From cc59d8dc93a571aeacca1ae59ecbddda3f52aff9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Thu, 6 Oct 2022 13:59:01 +0200 Subject: [PATCH] Update verilator top level module to match rom module changes --- hw/application_fpga/tb/application_fpga_vsim.v | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/application_fpga/tb/application_fpga_vsim.v b/hw/application_fpga/tb/application_fpga_vsim.v index f17fa67..1212aeb 100644 --- a/hw/application_fpga/tb/application_fpga_vsim.v +++ b/hw/application_fpga/tb/application_fpga_vsim.v @@ -222,9 +222,6 @@ module application_fpga( rom rom_inst( - .clk(clk), - .reset_n(reset_n), - .cs(rom_cs), .address(rom_address), .read_data(rom_read_data),