Doc: Add README for the clock and reset core.

Signed-off-by: Joachim Strömbergson <joachim@assured.se>

hw/application_fpga/core/clk_reset_gen/README.md

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+# clk_reset_gen
+Generator for system clock and system reset for the Tkey design.
+
+
+## Introduction
+This core implements the FPGA internal clock generator. The core also
+implements the reset circuitry for the FPGA design.
+
+
+## API
+The core does not have an API.
+
+
+## Implementation Details
+### Clock generation
+The clock is generated by the FPGA internal High frequency oscillator
+SB_HFOSC. The oscillator is configured to run at 12 MHz
+
+The oscillator drives the internal PLL SB_PLL40_CORE. The PLL
+parameters are hard coded to generate the target system frequency. The
+icestorm tool iceppl can be used to generate the appropriate DIVR,
+DIVF and DIVQ parameters to generate the target clock frequency given
+the frequency of the high speed oscillator.
+
+The output from the PLL is fed into an instance of a global buffer
+SB_GB. The global buffer drives the clock out to all clocked elements
+in the design.
+
+
+### Reset
+The reset is a simple register and a counter. When the FPGA chip reset
+is released (which means that the FPGA has been configured by the
+bitstream) the reset logic holds the design reset register low for
+RESET_CYCLES number of cycles. The reset registers is then released
+(set to one).