From c9f5173c1852373232e738e11e4a897ecc19ce22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Tue, 20 Aug 2024 13:23:44 +0200 Subject: [PATCH] Doc: Add README for the clock and reset core. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim Strömbergson --- .../core/clk_reset_gen/README.md | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 hw/application_fpga/core/clk_reset_gen/README.md diff --git a/hw/application_fpga/core/clk_reset_gen/README.md b/hw/application_fpga/core/clk_reset_gen/README.md new file mode 100644 index 0000000..0c6f0a2 --- /dev/null +++ b/hw/application_fpga/core/clk_reset_gen/README.md @@ -0,0 +1,35 @@ +# clk_reset_gen +Generator for system clock and system reset for the Tkey design. + + +## Introduction +This core implements the FPGA internal clock generator. The core also +implements the reset circuitry for the FPGA design. + + +## API +The core does not have an API. + + +## Implementation Details +### Clock generation +The clock is generated by the FPGA internal High frequency oscillator +SB_HFOSC. The oscillator is configured to run at 12 MHz + +The oscillator drives the internal PLL SB_PLL40_CORE. The PLL +parameters are hard coded to generate the target system frequency. The +icestorm tool iceppl can be used to generate the appropriate DIVR, +DIVF and DIVQ parameters to generate the target clock frequency given +the frequency of the high speed oscillator. + +The output from the PLL is fed into an instance of a global buffer +SB_GB. The global buffer drives the clock out to all clocked elements +in the design. + + +### Reset +The reset is a simple register and a counter. When the FPGA chip reset +is released (which means that the FPGA has been configured by the +bitstream) the reset logic holds the design reset register low for +RESET_CYCLES number of cycles. The reset registers is then released +(set to one).