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Remove API access to current prescaler value

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This commit is contained in:
Joachim Strömbergson 2022-10-06 15:56:13 +02:00
parent cc59d8dc93
commit c90771fe19
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GPG Key ID: 865B8A548EA61679
3 changed files with 3 additions and 9 deletions
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4
hw/application_fpga/core/timer/rtl/timer.v
View File

@ -72,7 +72,6 @@ module timer(
reg tmp_ready;
wire core_ready;
wire [31 : 0] core_curr_prescaler;
wire [31 : 0] core_curr_timer;
@ -93,7 +92,6 @@ module timer(
.timer_value(timer_reg),
.start(start_reg),
.stop(stop_reg),
.curr_prescaler(core_curr_prescaler),
.curr_timer(core_curr_timer),
.ready(core_ready)
);
@ -178,7 +176,7 @@ module timer(
end
if (address == ADDR_PRESCALER) begin
tmp_read_data = core_curr_prescaler;
tmp_read_data = prescaler_reg;
end
if (address == ADDR_TIMER) begin

2
hw/application_fpga/core/timer/rtl/timer_core.v
View File

@ -22,7 +22,6 @@ module timer_core(
input wire start,
input wire stop,
output wire [31 : 0] curr_prescaler,
output wire [31 : 0] curr_timer,
output wire ready
@ -65,7 +64,6 @@ module timer_core(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign curr_prescaler = prescaler_reg;
assign curr_timer = timer_reg;
assign ready = ready_reg;

2
hw/application_fpga/core/timer/tb/tb_timer_core.v
View File

@ -39,7 +39,6 @@ module tb_timer_core();
reg tb_stop;
reg [31 : 0] tb_prescaler;
reg [31 : 0] tb_timer;
wire [31 : 0] tb_curr_prescaler;
wire [31 : 0] tb_curr_timer;
wire tb_ready;
@ -54,7 +53,6 @@ module tb_timer_core();
.timer_value(tb_timer),
.start(tb_start),
.stop(tb_stop),
.curr_prescaler(tb_curr_prescaler),
.curr_timer(tb_curr_timer),
.ready(tb_ready)
);