From c90771fe1970884e7f4710e9bae72d842b226f9f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= <joachim@assured.se>
Date: Thu, 6 Oct 2022 15:56:13 +0200
Subject: [PATCH] Remove API access to current prescaler value

---
 hw/application_fpga/core/timer/rtl/timer.v        | 4 +---
 hw/application_fpga/core/timer/rtl/timer_core.v   | 6 ++----
 hw/application_fpga/core/timer/tb/tb_timer_core.v | 2 --
 3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/hw/application_fpga/core/timer/rtl/timer.v b/hw/application_fpga/core/timer/rtl/timer.v
index 034c841..9a44e77 100644
--- a/hw/application_fpga/core/timer/rtl/timer.v
+++ b/hw/application_fpga/core/timer/rtl/timer.v
@@ -72,7 +72,6 @@ module timer(
   reg           tmp_ready;
 
   wire          core_ready;
-  wire [31 : 0] core_curr_prescaler;
   wire [31 : 0] core_curr_timer;
 
 
@@ -93,7 +92,6 @@ module timer(
                   .timer_value(timer_reg),
                   .start(start_reg),
                   .stop(stop_reg),
-		  .curr_prescaler(core_curr_prescaler),
 		  .curr_timer(core_curr_timer),
                   .ready(core_ready)
                  );
@@ -178,7 +176,7 @@ module timer(
 	  end
 
 	  if (address == ADDR_PRESCALER) begin
-	    tmp_read_data = core_curr_prescaler;
+	    tmp_read_data = prescaler_reg;
 	  end
 
 	  if (address == ADDR_TIMER) begin
diff --git a/hw/application_fpga/core/timer/rtl/timer_core.v b/hw/application_fpga/core/timer/rtl/timer_core.v
index 3b109c0..226a964 100644
--- a/hw/application_fpga/core/timer/rtl/timer_core.v
+++ b/hw/application_fpga/core/timer/rtl/timer_core.v
@@ -22,7 +22,6 @@ module timer_core(
                   input wire           start,
                   input wire           stop,
 
-                  output wire [31 : 0] curr_prescaler,
                   output wire [31 : 0] curr_timer,
 
                   output wire          ready
@@ -65,9 +64,8 @@ module timer_core(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
-  assign curr_prescaler = prescaler_reg;
-  assign curr_timer     = timer_reg;
-  assign ready  = ready_reg;
+  assign curr_timer = timer_reg;
+  assign ready      = ready_reg;
 
 
   //----------------------------------------------------------------
diff --git a/hw/application_fpga/core/timer/tb/tb_timer_core.v b/hw/application_fpga/core/timer/tb/tb_timer_core.v
index b2f264d..730c55b 100644
--- a/hw/application_fpga/core/timer/tb/tb_timer_core.v
+++ b/hw/application_fpga/core/timer/tb/tb_timer_core.v
@@ -39,7 +39,6 @@ module tb_timer_core();
   reg           tb_stop;
   reg  [31 : 0] tb_prescaler;
   reg  [31 : 0] tb_timer;
-  wire [31 : 0] tb_curr_prescaler;
   wire [31 : 0] tb_curr_timer;
   wire          tb_ready;
 
@@ -54,7 +53,6 @@ module tb_timer_core();
 		 .timer_value(tb_timer),
 		 .start(tb_start),
 		 .stop(tb_stop),
-		 .curr_prescaler(tb_curr_prescaler),
 		 .curr_timer(tb_curr_timer),
 		 .ready(tb_ready)
                 );