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Build: Don't depend on uds.hex and udi.hex

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synth.json shouldn't depend on uds.hex and udi.hex because that
triggers a complete rebuild of the bitstream if the UDI or UDS are
changed.

Instead, we want only the application_fpga.asc to depend on them, so
we can patch in the UDS and UDI with tools/patch_uds_udi.py in an
existing application_fpga_par.json.
This commit is contained in:
Michael Cardell Widerkrantz 2025-01-20 14:48:53 +01:00
parent 66888a3756
commit a5ed3cfaa9
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GPG Key ID: D3DB3DDF57E704E5
1 changed files with 1 additions and 2 deletions
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3
hw/application_fpga/Makefile
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@ -353,8 +353,7 @@ tb:
YOSYS_FLAG ?= YOSYS_FLAG ?=
synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \ synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
$(P)/data/uds.hex $(P)/data/udi.hex
$(YOSYS_PATH)yosys \ $(YOSYS_PATH)yosys \
-v3 \ -v3 \
-l synth.txt \ -l synth.txt \