From a5ed3cfaa94bfeea074c4f8621be857d80095427 Mon Sep 17 00:00:00 2001 From: Michael Cardell Widerkrantz Date: Mon, 20 Jan 2025 14:48:53 +0100 Subject: [PATCH] Build: Don't depend on uds.hex and udi.hex synth.json shouldn't depend on uds.hex and udi.hex because that triggers a complete rebuild of the bitstream if the UDI or UDS are changed. Instead, we want only the application_fpga.asc to depend on them, so we can patch in the UDS and UDI with tools/patch_uds_udi.py in an existing application_fpga_par.json. --- hw/application_fpga/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile index 31a8f90..097ba76 100644 --- a/hw/application_fpga/Makefile +++ b/hw/application_fpga/Makefile @@ -353,8 +353,7 @@ tb: YOSYS_FLAG ?= -synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex \ - $(P)/data/uds.hex $(P)/data/udi.hex +synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex $(YOSYS_PATH)yosys \ -v3 \ -l synth.txt \