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Cleanup, and use fifo_empty to indicate data available

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Joachim Strömbergson 2022-10-28 13:12:47 +02:00
parent 24d8680772
commit 8061491f6e
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1 changed files with 2 additions and 3 deletions
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5
hw/application_fpga/core/uart/rtl/uart_fifo.v
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@ -84,9 +84,8 @@ module uart_fifo(
//---------------------------------------------------------------- //----------------------------------------------------------------
// Concurrent connectivity for ports etc. // Concurrent connectivity for ports etc.
//---------------------------------------------------------------- //----------------------------------------------------------------
assign in_ack = in_ack_reg; assign in_ack = in_ack_reg;
assign out_syn = ~fifo_empty;
assign out_syn = |byte_ctr_reg;
assign out_data = fifo_mem[out_ptr_reg]; assign out_data = fifo_mem[out_ptr_reg];