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Cleanup, and use fifo_empty to indicate data available
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@ -84,9 +84,8 @@ module uart_fifo(
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// Concurrent connectivity for ports etc.
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// Concurrent connectivity for ports etc.
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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assign in_ack = in_ack_reg;
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assign in_ack = in_ack_reg;
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assign out_syn = ~fifo_empty;
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assign out_syn = |byte_ctr_reg;
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assign out_data = fifo_mem[out_ptr_reg];
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assign out_data = fifo_mem[out_ptr_reg];
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