From 8061491f6e4af07b00782278a99c6d87cafceee9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Str=C3=B6mbergson?= Date: Fri, 28 Oct 2022 13:12:47 +0200 Subject: [PATCH] Cleanup, and use fifo_empty to indicate data available --- hw/application_fpga/core/uart/rtl/uart_fifo.v | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/application_fpga/core/uart/rtl/uart_fifo.v b/hw/application_fpga/core/uart/rtl/uart_fifo.v index 950f03a..e620bb0 100644 --- a/hw/application_fpga/core/uart/rtl/uart_fifo.v +++ b/hw/application_fpga/core/uart/rtl/uart_fifo.v @@ -84,9 +84,8 @@ module uart_fifo( //---------------------------------------------------------------- // Concurrent connectivity for ports etc. //---------------------------------------------------------------- - assign in_ack = in_ack_reg; - - assign out_syn = |byte_ctr_reg; + assign in_ack = in_ack_reg; + assign out_syn = ~fifo_empty; assign out_data = fifo_mem[out_ptr_reg];