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FPGA: Add --freq constraint to nextpnr

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-24 11:40:51 +02:00 committed by Daniel Jobson
parent 75b028505f
commit 7f93b7817b
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GPG Key ID: 3707A9DBF4BB8F1A
1 changed files with 5 additions and 1 deletions
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6
hw/application_fpga/Makefile
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@ -26,6 +26,10 @@ YOSYS_PATH ?=
NEXTPNR_PATH ?= NEXTPNR_PATH ?=
ICESTORM_PATH ?= ICESTORM_PATH ?=
# FPGA target frequency. Should be in sync with the clock frequency
# given by the parameters to the PLL in rtl/clk_reset_gen.v
TARGET_FREQ ?= 21
# Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16 # Size in 32-bit words, must be divisible by 256 (pairs of EBRs, because 16
# bits wide; an EBR is 128 32-bits words) # bits wide; an EBR is 128 32-bits words)
BRAM_FW_SIZE ?= 1536 BRAM_FW_SIZE ?= 1536
@ -256,7 +260,7 @@ synth.json: $(FPGA_SRC) $(VERILOG_SRCS) bram_fw.hex $(P)/data/uds.hex $(P)/data/
$(filter %.v, $^) $(filter %.v, $^)
application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE) application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
$(NEXTPNR_PATH)nextpnr-ice40 --ignore-loops --up5k --package sg48 --json $< \ $(NEXTPNR_PATH)nextpnr-ice40 --freq $(TARGET_FREQ) --ignore-loops --up5k --package sg48 --json $< \
--pcf $(P)/data/$(PIN_FILE) --write $@ --pcf $(P)/data/$(PIN_FILE) --write $@
application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex application_fpga.asc: application_fpga_par.json $(P)/data/uds.hex $(P)/data/udi.hex