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fpga: Update seed to reach 24 MHz

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Mikael Ågren 2025-05-12 18:41:12 +02:00
parent 37fc925795
commit 7f6471c9b2
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1 changed files with 1 additions and 1 deletions
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hw/application_fpga/Makefile
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@ -396,7 +396,7 @@ synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE) application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
$(NEXTPNR_PATH)nextpnr-ice40 \ $(NEXTPNR_PATH)nextpnr-ice40 \
-l application_fpga_par.txt \ -l application_fpga_par.txt \
--seed 9416596747216415304 \ --seed 12781509045096007008 \
--freq $(TARGET_FREQ) \ --freq $(TARGET_FREQ) \
--ignore-loops \ --ignore-loops \
--up5k \ --up5k \