From 7f6471c9b2f74bcb8cab455cc3e347f5fde87b9c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mikael=20=C3=85gren?= <mikael@tillitis.se>
Date: Mon, 12 May 2025 18:41:12 +0200
Subject: [PATCH] fpga: Update seed to reach 24 MHz

---
 hw/application_fpga/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/application_fpga/Makefile b/hw/application_fpga/Makefile
index 786bd6d..8db2d7d 100644
--- a/hw/application_fpga/Makefile
+++ b/hw/application_fpga/Makefile
@@ -396,7 +396,7 @@ synth.json: $(FPGA_VERILOG_SRCS) $(VERILOG_SRCS) $(PICORV32_SRCS) bram_fw.hex
 application_fpga_par.json: synth.json $(P)/data/$(PIN_FILE)
 	$(NEXTPNR_PATH)nextpnr-ice40 \
 		-l application_fpga_par.txt \
-		--seed 9416596747216415304 \
+		--seed 12781509045096007008 \
 		--freq $(TARGET_FREQ) \
 		--ignore-loops \
 		--up5k \