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FPGA: Increase clock frequency to 21 MHz

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Signed-off-by: Joachim Strömbergson <joachim@assured.se>
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Joachim Strömbergson 2024-06-17 15:28:57 +02:00 • committed by Daniel Jobson
parent 00599549e3
commit 75b028505f
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GPG key ID: 3707A9DBF4BB8F1A
3 changed files with 9 additions and 9 deletions
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6
hw/application_fpga/core/uart/rtl/uart.v
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@ -83,10 +83,10 @@ module uart(
// The default bit rate is based on target clock frequency
// divided by the bit rate times in order to hit the
// center of the bits. I.e.
// Clock: 18 MHz, 62500 bps
// Divisor = 18E6 / 62500 = 288
// Clock: 21 MHz, 62500 bps
// Divisor = 21E6 / 62500 = 336
// This also satisfies 1E6 % bps == 0 for the CH552 MCU used for USB-serial
localparam DEFAULT_BIT_RATE = 16'd288;
localparam DEFAULT_BIT_RATE = 16'd336;
localparam DEFAULT_DATA_BITS = 4'h8;
localparam DEFAULT_STOP_BITS = 2'h1;