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fpga: Add extra access control on UDS

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Restrict access to UDS when we have exited firmware the first time.

Co-authored-by: Michael Cardell Widerkrantz <mc@tillitis.se>
This commit is contained in:
Mikael Ågren 2025-02-24 09:49:30 +01:00
parent 77fc5cf578
commit 7554787678
No known key found for this signature in database
GPG Key ID: E02DA3D397792C46
4 changed files with 19 additions and 14 deletions
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2
hw/application_fpga/core/tk1/rtl/tk1.v
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@ -21,6 +21,7 @@ module tk1 #(
input wire cpu_trap, input wire cpu_trap,
output wire app_mode, output wire app_mode,
output wire fw_startup_done,
input wire [31 : 0] cpu_addr, input wire [31 : 0] cpu_addr,
input wire cpu_instr, input wire cpu_instr,
@ -184,6 +185,7 @@ module tk1 #(
assign ready = tmp_ready; assign ready = tmp_ready;
assign app_mode = fw_startup_done_reg & ~syscall; assign app_mode = fw_startup_done_reg & ~syscall;
assign fw_startup_done = fw_startup_done_reg;
assign force_trap = force_trap_reg; assign force_trap = force_trap_reg;

5
hw/application_fpga/core/uds/rtl/uds.v
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@ -17,8 +17,7 @@ module uds (
input wire clk, input wire clk,
input wire reset_n, input wire reset_n,
input wire app_mode, input wire en,
input wire cs, input wire cs,
input wire [ 2 : 0] address, input wire [ 2 : 0] address,
output wire [31 : 0] read_data, output wire [31 : 0] read_data,
@ -89,7 +88,7 @@ module uds (
if (cs) begin if (cs) begin
tmp_ready = 1'h1; tmp_ready = 1'h1;
if (!app_mode) begin if (en) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1; uds_rd_we = 1'h1;
end end

4
hw/application_fpga/rtl/application_fpga.v
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@ -154,6 +154,7 @@ module application_fpga (
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire app_mode; wire app_mode;
wire fw_startup_done;
wire force_trap; wire force_trap;
wire [14 : 0] ram_addr_rand; wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand; wire [31 : 0] ram_data_rand;
@ -294,7 +295,7 @@ module application_fpga (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.app_mode(app_mode), .en(~fw_startup_done),
.cs(uds_cs), .cs(uds_cs),
.address(uds_address), .address(uds_address),
@ -341,6 +342,7 @@ module application_fpga (
.reset_n(reset_n), .reset_n(reset_n),
.app_mode(app_mode), .app_mode(app_mode),
.fw_startup_done(fw_startup_done),
.cpu_addr (cpu_addr), .cpu_addr (cpu_addr),
.cpu_instr (cpu_instr), .cpu_instr (cpu_instr),

4
hw/application_fpga/tb/application_fpga_sim.v
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@ -166,6 +166,7 @@ module application_fpga_sim (
wire [31 : 0] tk1_read_data; wire [31 : 0] tk1_read_data;
wire tk1_ready; wire tk1_ready;
wire app_mode; wire app_mode;
wire fw_startup_done;
wire force_trap; wire force_trap;
wire [14 : 0] ram_addr_rand; wire [14 : 0] ram_addr_rand;
wire [31 : 0] ram_data_rand; wire [31 : 0] ram_data_rand;
@ -305,7 +306,7 @@ module application_fpga_sim (
.clk(clk), .clk(clk),
.reset_n(reset_n), .reset_n(reset_n),
.app_mode(app_mode), .en(~fw_startup_done),
.cs(uds_cs), .cs(uds_cs),
.address(uds_address), .address(uds_address),
@ -354,6 +355,7 @@ module application_fpga_sim (
.reset_n(reset_n), .reset_n(reset_n),
.app_mode(app_mode), .app_mode(app_mode),
.fw_startup_done(fw_startup_done),
.cpu_addr (cpu_addr), .cpu_addr (cpu_addr),
.cpu_instr (cpu_instr), .cpu_instr (cpu_instr),