diff --git a/hw/application_fpga/core/tk1/rtl/tk1.v b/hw/application_fpga/core/tk1/rtl/tk1.v
index 8bd4732..0aba642 100644
--- a/hw/application_fpga/core/tk1/rtl/tk1.v
+++ b/hw/application_fpga/core/tk1/rtl/tk1.v
@@ -21,6 +21,7 @@ module tk1 #(
 
     input  wire cpu_trap,
     output wire app_mode,
+    output wire fw_startup_done,
 
     input  wire [31 : 0] cpu_addr,
     input  wire          cpu_instr,
@@ -180,20 +181,21 @@ module tk1 #(
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
   //----------------------------------------------------------------
-  assign read_data     = tmp_read_data;
-  assign ready         = tmp_ready;
+  assign read_data       = tmp_read_data;
+  assign ready           = tmp_ready;
 
-  assign app_mode      = fw_startup_done_reg & ~syscall;
+  assign app_mode        = fw_startup_done_reg & ~syscall;
+  assign fw_startup_done = fw_startup_done_reg;
 
-  assign force_trap    = force_trap_reg;
+  assign force_trap      = force_trap_reg;
 
-  assign gpio3         = gpio3_reg;
-  assign gpio4         = gpio4_reg;
+  assign gpio3           = gpio3_reg;
+  assign gpio4           = gpio4_reg;
 
-  assign ram_addr_rand = ram_addr_rand_reg;
-  assign ram_data_rand = ram_data_rand_reg;
+  assign ram_addr_rand   = ram_addr_rand_reg;
+  assign ram_data_rand   = ram_data_rand_reg;
 
-  assign system_reset  = system_reset_reg;
+  assign system_reset    = system_reset_reg;
 
   //----------------------------------------------------------------
   // Module instance.
diff --git a/hw/application_fpga/core/uds/rtl/uds.v b/hw/application_fpga/core/uds/rtl/uds.v
index 4175a10..8c8f1a3 100644
--- a/hw/application_fpga/core/uds/rtl/uds.v
+++ b/hw/application_fpga/core/uds/rtl/uds.v
@@ -17,8 +17,7 @@ module uds (
     input wire clk,
     input wire reset_n,
 
-    input wire app_mode,
-
+    input  wire          en,
     input  wire          cs,
     input  wire [ 2 : 0] address,
     output wire [31 : 0] read_data,
@@ -89,7 +88,7 @@ module uds (
     if (cs) begin
       tmp_ready = 1'h1;
 
-      if (!app_mode) begin
+      if (en) begin
         if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
           uds_rd_we = 1'h1;
         end
diff --git a/hw/application_fpga/rtl/application_fpga.v b/hw/application_fpga/rtl/application_fpga.v
index c46b5a0..f7d21ea 100644
--- a/hw/application_fpga/rtl/application_fpga.v
+++ b/hw/application_fpga/rtl/application_fpga.v
@@ -154,6 +154,7 @@ module application_fpga (
   wire [31 : 0] tk1_read_data;
   wire          tk1_ready;
   wire          app_mode;
+  wire          fw_startup_done;
   wire          force_trap;
   wire [14 : 0] ram_addr_rand;
   wire [31 : 0] ram_data_rand;
@@ -294,7 +295,7 @@ module application_fpga (
       .clk(clk),
       .reset_n(reset_n),
 
-      .app_mode(app_mode),
+      .en(~fw_startup_done),
 
       .cs(uds_cs),
       .address(uds_address),
@@ -341,6 +342,7 @@ module application_fpga (
       .reset_n(reset_n),
 
       .app_mode(app_mode),
+      .fw_startup_done(fw_startup_done),
 
       .cpu_addr  (cpu_addr),
       .cpu_instr (cpu_instr),
diff --git a/hw/application_fpga/tb/application_fpga_sim.v b/hw/application_fpga/tb/application_fpga_sim.v
index 2be8bd5..a3314a7 100644
--- a/hw/application_fpga/tb/application_fpga_sim.v
+++ b/hw/application_fpga/tb/application_fpga_sim.v
@@ -166,6 +166,7 @@ module application_fpga_sim (
   wire [31 : 0] tk1_read_data;
   wire          tk1_ready;
   wire          app_mode;
+  wire          fw_startup_done;
   wire          force_trap;
   wire [14 : 0] ram_addr_rand;
   wire [31 : 0] ram_data_rand;
@@ -305,7 +306,7 @@ module application_fpga_sim (
       .clk(clk),
       .reset_n(reset_n),
 
-      .app_mode(app_mode),
+      .en(~fw_startup_done),
 
       .cs(uds_cs),
       .address(uds_address),
@@ -354,6 +355,7 @@ module application_fpga_sim (
       .reset_n(reset_n),
 
       .app_mode(app_mode),
+      .fw_startup_done(fw_startup_done),
 
       .cpu_addr  (cpu_addr),
       .cpu_instr (cpu_instr),