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fpga: Add extra access control on UDS

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Restrict access to UDS when we have exited firmware the first time.

Co-authored-by: Michael Cardell Widerkrantz <mc@tillitis.se>
This commit is contained in:
Mikael Ågren 2025-02-24 09:49:30 +01:00
parent 77fc5cf578
commit 7554787678
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GPG key ID: E02DA3D397792C46
4 changed files with 19 additions and 14 deletions
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20
hw/application_fpga/core/tk1/rtl/tk1.v
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@ -21,6 +21,7 @@ module tk1 #(
input wire cpu_trap,
output wire app_mode,
output wire fw_startup_done,
input wire [31 : 0] cpu_addr,
input wire cpu_instr,
@ -180,20 +181,21 @@ module tk1 #(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
assign ready = tmp_ready;
assign read_data = tmp_read_data;
assign ready = tmp_ready;
assign app_mode = fw_startup_done_reg & ~syscall;
assign app_mode = fw_startup_done_reg & ~syscall;
assign fw_startup_done = fw_startup_done_reg;
assign force_trap = force_trap_reg;
assign force_trap = force_trap_reg;
assign gpio3 = gpio3_reg;
assign gpio4 = gpio4_reg;
assign gpio3 = gpio3_reg;
assign gpio4 = gpio4_reg;
assign ram_addr_rand = ram_addr_rand_reg;
assign ram_data_rand = ram_data_rand_reg;
assign ram_addr_rand = ram_addr_rand_reg;
assign ram_data_rand = ram_data_rand_reg;
assign system_reset = system_reset_reg;
assign system_reset = system_reset_reg;
//----------------------------------------------------------------
// Module instance.

5
hw/application_fpga/core/uds/rtl/uds.v
View file

@ -17,8 +17,7 @@ module uds (
input wire clk,
input wire reset_n,
input wire app_mode,
input wire en,
input wire cs,
input wire [ 2 : 0] address,
output wire [31 : 0] read_data,
@ -89,7 +88,7 @@ module uds (
if (cs) begin
tmp_ready = 1'h1;
if (!app_mode) begin
if (en) begin
if (uds_rd_reg[address[2 : 0]] == 1'h0) begin
uds_rd_we = 1'h1;
end